From 0140fe27e2f80464d640b346ac2f9b893d791a9b Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Mon, 10 Jun 2024 13:22:47 +0100
Subject: [PATCH] hdl._dsl: forbid empty string as submodule name.

This is semantically ambiguous and breaks the RTLIL emitter.

Fixes #1209.
---
 amaranth/hdl/_dsl.py  | 2 ++
 tests/test_hdl_dsl.py | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/amaranth/hdl/_dsl.py b/amaranth/hdl/_dsl.py
index a73f20f..c66df2e 100644
--- a/amaranth/hdl/_dsl.py
+++ b/amaranth/hdl/_dsl.py
@@ -654,6 +654,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         if name == None:
             self._anon_submodules.append((submodule, src_loc))
         else:
+            if name == "":
+                raise NameError("Submodule name must not be empty")
             if name in self._named_submodules:
                 raise NameError(f"Submodule named '{name}' already exists")
             self._named_submodules[name] = (submodule, src_loc)
diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py
index a255ff6..ecbed9d 100644
--- a/tests/test_hdl_dsl.py
+++ b/tests/test_hdl_dsl.py
@@ -887,6 +887,12 @@ class DSLTestCase(FHDLTestCase):
         with self.assertRaisesRegex(NameError, r"^Submodule named 'foo' already exists$"):
             m1.submodules.foo = m2
 
+    def test_submodule_named_empty(self):
+        m1 = Module()
+        m2 = Module()
+        with self.assertRaisesRegex(NameError, r"^Submodule name must not be empty$"):
+            m1.submodules[""] = m2
+
     def test_submodule_get(self):
         m1 = Module()
         m2 = Module()