From 0169d47365854ef836a9762463fe041fd5b73b8d Mon Sep 17 00:00:00 2001 From: Catherine Date: Thu, 16 Dec 2021 08:03:53 +0000 Subject: [PATCH] docs/changes: add simulation-related changes. --- docs/changes.rst | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/docs/changes.rst b/docs/changes.rst index 7c48187..1e2745d 100644 --- a/docs/changes.rst +++ b/docs/changes.rst @@ -25,8 +25,9 @@ Apply the following changes to code written against nMigen 0.2 to migrate it to * Update board definitions using :class:`vendor.lattice_machxo2.LatticeMachXO2Platform` to use :class:`vendor.lattice_machxo_2_3l.LatticeMachXO2Platform`. * Update board definitions using :class:`vendor.xilinx_spartan_3_6.XilinxSpartan3APlatform`, :class:`vendor.xilinx_spartan_3_6.XilinxSpartan6Platform`, :class:`vendor.xilinx_7series.Xilinx7SeriesPlatform`, :class:`vendor.xilinx_ultrascale.XilinxUltrascalePlatform` to use :class:`vendor.xilinx.XilinxPlatform`. * Switch uses of :class:`hdl.ast.UserValue` to :class:`ValueCastable`; note that :class:`ValueCastable` does not inherit from :class:`Value`, and inheriting from :class:`Value` is not supported. -* Remove uses of :class:`test.utils.FHDLTestCase` and vendor the implementation of :class:`test.utils.FHDLTestCase.assertFormal` if necessary. +* Switch uses of :mod:`back.pysim` to :mod:`sim`. * Add an explicit ``ports=`` argument to uses of :func:`back.rtlil.convert` and :func:`back.verilog.convert` if missing. +* Remove uses of :class:`test.utils.FHDLTestCase` and vendor the implementation of :class:`test.utils.FHDLTestCase.assertFormal` if necessary. While code that uses the features listed as deprecated below will work in Amaranth 0.3, they will be removed in the next version. @@ -65,8 +66,11 @@ Toolchain changes * Added: Backend emits Yosys enumeration attributes for :ref:`enumeration-shaped ` signals. * Added: If a compatible Yosys version is not installed, :mod:`back.verilog` will fall back to the `amaranth-yosys `_ PyPI package. The package can be :ref:`installed ` as ``amaranth[builtin-yosys]`` to ensure this dependency is available. * Added: :mod:`back.cxxrtl`. +* Added: :mod:`sim`, a simulator interface with support for multiple simulation backends. +* Deprecated: :mod:`back.pysim`; use :mod:`sim` instead. * Removed: The ``with Simulator(fragment, ...) as sim:`` form. * Removed: :meth:`sim.Simulator.add_process` with a generator argument. +* Deprecated: :meth:`sim.Simulator.step`; use :meth:`sim.Simulator.advance` instead. * Added: :meth:`build.BuildPlan.execute_remote_ssh`. * Deprecated: :class:`test.utils.FHDLTestCase`, with no replacement. * Deprecated: :func:`back.rtlil.convert()` and :func:`back.verilog.convert()` without an explicit `ports=` argument.