diff --git a/amaranth/sim/_pyrtl.py b/amaranth/sim/_pyrtl.py
index b18f99f..7e52eea 100644
--- a/amaranth/sim/_pyrtl.py
+++ b/amaranth/sim/_pyrtl.py
@@ -378,7 +378,7 @@ class _StatementCompiler(StatementVisitor, _Compiler):
                         value = int("".join("0" if b == "-" else  b  for b in pattern), 2)
                         gen_checks.append(f"{value} == ({mask} & {gen_test})")
                     else:
-                        value = int(pattern, 2)
+                        value = int(pattern or "0", 2)
                         gen_checks.append(f"{value} == {gen_test}")
             if index == 0:
                 self.emitter.append(f"if {' or '.join(gen_checks)}:")
diff --git a/tests/test_sim.py b/tests/test_sim.py
index 01e55d3..7950fe6 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -1064,6 +1064,18 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         m.d.comb += a.eq(op)
         Simulator(m)
 
+    def test_switch_zero(self):
+        m = Module()
+        a = Signal(0)
+        o = Signal()
+        with m.Switch(a):
+            with m.Case(""):
+                m.d.comb += o.eq(1)
+        with self.assertSimulation(m) as sim:
+            def process():
+                self.assertEqual((yield o), 1)
+            sim.add_testbench(process)
+
 
 class SimulatorRegressionTestCase(FHDLTestCase):
     def test_bug_325(self):