diff --git a/amaranth/vendor/_lattice_machxo_2_3l.py b/amaranth/vendor/_lattice_machxo_2_3l.py index ae94940..d137138 100644 --- a/amaranth/vendor/_lattice_machxo_2_3l.py +++ b/amaranth/vendor/_lattice_machxo_2_3l.py @@ -1,9 +1,56 @@ from abc import abstractmethod from ..hdl import * +from ..lib import io, wiring from ..build import * +# MachXO[23] I/O buffers are identical to ECP5 except for DDR. + +from ._lattice_ecp5 import InnerBuffer, IOBuffer, FFBuffer, _make_oereg + + +class DDRBuffer(io.DDRBuffer): + def elaborate(self, platform): + m = Module() + + m.submodules.buf = buf = InnerBuffer(self.direction, self.port) + inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert)) + + if self.direction is not io.Direction.Output: + i0_inv = Signal(len(self.port)) + i1_inv = Signal(len(self.port)) + for bit in range(len(self.port)): + m.submodules.i_ddr = Instance("IDDRXE", + i_SCLK=ClockSignal(self.i_domain), + i_RST=Const(0), + i_D=buf.i[bit], + o_Q0=i0_inv[bit], + o_Q1=i1_inv[bit], + ) + m.d.comb += self.i[0].eq(i0_inv ^ inv_mask) + m.d.comb += self.i[1].eq(i1_inv ^ inv_mask) + + if self.direction is not io.Direction.Input: + o0_inv = Signal(len(self.port)) + o1_inv = Signal(len(self.port)) + m.d.comb += [ + o0_inv.eq(self.o[0] ^ inv_mask), + o1_inv.eq(self.o[1] ^ inv_mask), + ] + for bit in range(len(self.port)): + m.submodules.o_ddr = Instance("ODDRXE", + i_SCLK=ClockSignal(self.o_domain), + i_RST=Const(0), + i_D0=o0_inv[bit], + i_D1=o1_inv[bit], + o_Q=buf.o[bit], + ) + _make_oereg(m, self.o_domain, ~self.oe, buf.t) + + return m + + # MachXO2 and MachXO3L primitives are the same. Handle both using # one class and expose user-aliases for convenience. class LatticeMachXO2Or3LPlatform(TemplatedPlatform): @@ -209,232 +256,20 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform): m.d.comb += ClockSignal("sync").eq(clk_i) return m - _single_ended_io_types = [ - "PCI33", "LVTTL33", "LVCMOS33", "LVCMOS25", "LVCMOS18", "LVCMOS15", "LVCMOS12", - "LVCMOS25R33", "LVCMOS18R33", "LVCMOS18R25", "LVCMOS15R33", "LVCMOS15R25", "LVCMOS12R33", - "LVCMOS12R25", "LVCMOS10R33", "LVCMOS10R25", "SSTL25_I", "SSTL25_II", "SSTL18_I", - "SSTL18_II", "HSTL18_I", "HSTL18_II", - ] - _differential_io_types = [ - "LVDS25", "LVDS25E", "RSDS25", "RSDS25E", "BLVDS25", "BLVDS25E", "MLVDS25", "MLVDS25E", - "LVPECL33", "LVPECL33E", "SSTL25D_I", "SSTL25D_II", "SSTL18D_I", "SSTL18D_II", - "HSTL18D_I", "HSTL18D_II", "LVTTL33D", "LVCMOS33D", "LVCMOS25D", "LVCMOS18D", "LVCMOS15D", - "LVCMOS12D", "MIPI", - ] - - def should_skip_port_component(self, port, attrs, component): - # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at - # the PIOA or PIOC location, which is always the non-inverting pin. - if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n": - return True - return False - - def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False): - def get_ireg(clk, d, q): - for bit in range(len(q)): - m.submodules += Instance("IFS1P3DX", - i_SCLK=clk, - i_SP=Const(1), - i_CD=Const(0), - i_D=d[bit], - o_Q=q[bit] - ) - - def get_oreg(clk, d, q): - for bit in range(len(q)): - m.submodules += Instance("OFS1P3DX", - i_SCLK=clk, - i_SP=Const(1), - i_CD=Const(0), - i_D=d[bit], - o_Q=q[bit] - ) - - def get_iddr(sclk, d, q0, q1): - for bit in range(len(d)): - m.submodules += Instance("IDDRXE", - i_SCLK=sclk, - i_RST=Const(0), - i_D=d[bit], - o_Q0=q0[bit], o_Q1=q1[bit] - ) - - def get_oddr(sclk, d0, d1, q): - for bit in range(len(q)): - m.submodules += Instance("ODDRXE", - i_SCLK=sclk, - i_RST=Const(0), - i_D0=d0[bit], i_D1=d1[bit], - o_Q=q[bit] - ) - - def get_ineg(z, invert): - if invert: - a = Signal.like(z, name_suffix="_n") - m.d.comb += z.eq(~a) - return a - else: - return z - - def get_oneg(a, invert): - if invert: - z = Signal.like(a, name_suffix="_n") - m.d.comb += z.eq(~a) - return z - else: - return a - - if "i" in pin.dir: - if pin.xdr < 2: - pin_i = get_ineg(pin.i, i_invert) - elif pin.xdr == 2: - pin_i0 = get_ineg(pin.i0, i_invert) - pin_i1 = get_ineg(pin.i1, i_invert) - if "o" in pin.dir: - if pin.xdr < 2: - pin_o = get_oneg(pin.o, o_invert) - elif pin.xdr == 2: - pin_o0 = get_oneg(pin.o0, o_invert) - pin_o1 = get_oneg(pin.o1, o_invert) - - i = o = t = None - if "i" in pin.dir: - i = Signal(pin.width, name=f"{pin.name}_xdr_i") - if "o" in pin.dir: - o = Signal(pin.width, name=f"{pin.name}_xdr_o") - if pin.dir in ("oe", "io"): - t = Signal(1, name=f"{pin.name}_xdr_t") - - if pin.xdr == 0: - if "i" in pin.dir: - i = pin_i - if "o" in pin.dir: - o = pin_o - if pin.dir in ("oe", "io"): - t = ~pin.oe - elif pin.xdr == 1: - # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO. - if "i" in pin.dir: - get_ireg(pin.i_clk, i, pin_i) - if "o" in pin.dir: - get_oreg(pin.o_clk, pin_o, o) - if pin.dir in ("oe", "io"): - get_oreg(pin.o_clk, ~pin.oe, t) - elif pin.xdr == 2: - if "i" in pin.dir: - get_iddr(pin.i_clk, i, pin_i0, pin_i1) - if "o" in pin.dir: - get_oddr(pin.o_clk, pin_o0, pin_o1, o) - if pin.dir in ("oe", "io"): - # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO. - # It is not clear what is the recommended set of primitives for this task. - # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO. - get_oreg(pin.o_clk, ~pin.oe, t) + def get_io_buffer(self, buffer): + if isinstance(buffer, io.Buffer): + result = IOBuffer(buffer.direction, buffer.port) + elif isinstance(buffer, io.FFBuffer): + result = FFBuffer(buffer.direction, buffer.port) + elif isinstance(buffer, io.DDRBuffer): + result = DDRBuffer(buffer.direction, buffer.port) else: - assert False - - return (i, o, t) - - def get_input(self, pin, port, attrs, invert): - self._check_feature("single-ended input", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("IB", - i_I=port.io[bit], - o_O=i[bit] - ) - return m - - def get_output(self, pin, port, attrs, invert): - self._check_feature("single-ended output", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("OB", - i_I=o[bit], - o_O=port.io[bit] - ) - return m - - def get_tristate(self, pin, port, attrs, invert): - self._check_feature("single-ended tristate", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ", - i_T=t, - i_I=o[bit], - o_O=port.io[bit] - ) - return m - - def get_input_output(self, pin, port, attrs, invert): - self._check_feature("single-ended input/output", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("BB", - i_T=t, - i_I=o[bit], - o_O=i[bit], - io_B=port.io[bit] - ) - return m - - def get_diff_input(self, pin, port, attrs, invert): - self._check_feature("differential input", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("IB", - i_I=port.p[bit], - o_O=i[bit] - ) - return m - - def get_diff_output(self, pin, port, attrs, invert): - self._check_feature("differential output", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("OB", - i_I=o[bit], - o_O=port.p[bit], - ) - return m - - def get_diff_tristate(self, pin, port, attrs, invert): - self._check_feature("differential tristate", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("OBZ", - i_T=t, - i_I=o[bit], - o_O=port.p[bit], - ) - return m - - def get_diff_input_output(self, pin, port, attrs, invert): - self._check_feature("differential input/output", pin, attrs, - valid_xdrs=(0, 1, 2), valid_attrs=True) - m = Module() - i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert) - for bit in range(pin.width): - m.submodules[f"{pin.name}_{bit}"] = Instance("BB", - i_T=t, - i_I=o[bit], - o_O=i[bit], - io_B=port.p[bit], - ) - return m + raise TypeError(f"Unsupported buffer type {buffer!r}") # :nocov: + if buffer.direction is not io.Direction.Output: + result.i = buffer.i + if buffer.direction is not io.Direction.Input: + result.o = buffer.o + result.oe = buffer.oe + return result # CDC primitives are not currently specialized for MachXO2/MachXO3L.