diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index c0f7dae..cfb1b44 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -122,7 +122,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             }
             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
             report_timing_summary -file {{name}}_timing_synth.rpt
-            report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
+            report_utilization -hierarchical -file {{name}}_utilization_hierarchical_synth.rpt
             report_utilization -file {{name}}_utilization_synth.rpt
             opt_design
             place_design
diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index bc28ac2..1a2d391 100644
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -96,7 +96,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             }
             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
             report_timing_summary -file {{name}}_timing_synth.rpt
-            report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
+            report_utilization -hierarchical -file {{name}}_utilization_hierarchical_synth.rpt
             report_utilization -file {{name}}_utilization_synth.rpt
             opt_design
             place_design