diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py
index 3295ffb..f0b1902 100644
--- a/amaranth/back/rtlil.py
+++ b/amaranth/back/rtlil.py
@@ -529,8 +529,8 @@ class _RHSValueCompiler(_ValueCompiler):
             lhs_wire = self(lhs)
             rhs_wire = self(rhs)
         else:
+            lhs_bits = rhs_bits = max(lhs_bits + rhs_sign, rhs_bits + lhs_sign)
             lhs_sign = rhs_sign = True
-            lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
             lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
             rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
         res_bits, res_sign = value.shape()