diff --git a/tests/test_hdl_ast.py b/tests/test_hdl_ast.py
index 78c956d..9f550b1 100644
--- a/tests/test_hdl_ast.py
+++ b/tests/test_hdl_ast.py
@@ -561,7 +561,7 @@ class OperatorTestCase(FHDLTestCase):
         v = Const(0b101).all()
         self.assertEqual(repr(v), "(r& (const 3'd5))")
 
-    def test_xor(self):
+    def test_xor_value(self):
         v = Const(0b101).xor()
         self.assertEqual(repr(v), "(r^ (const 3'd5))")
 
diff --git a/tests/test_hdl_ir.py b/tests/test_hdl_ir.py
index 53e9054..c578bbe 100644
--- a/tests/test_hdl_ir.py
+++ b/tests/test_hdl_ir.py
@@ -424,7 +424,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
             None: SignalSet((ResetSignal("b_sync"),))
         }))
 
-    def test_domain_conflict_rename_drivers(self):
+    def test_domain_conflict_rename_drivers_before_creating_missing(self):
         cda = ClockDomain("sync")
         cdb = ClockDomain("sync")
         s = Signal()