diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 4a994fd..dbddd61 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -278,6 +278,9 @@ class _ValueCompilerState:
         self.ports[signal] = (len(self.ports), kind)
 
     def resolve(self, signal, prefix=None):
+        if len(signal) == 0:
+            return "{ }", "{ }"
+
         if signal in self.wires:
             return self.wires[signal]