diff --git a/amaranth/sim/_pyrtl.py b/amaranth/sim/_pyrtl.py
index fb18298..1545686 100644
--- a/amaranth/sim/_pyrtl.py
+++ b/amaranth/sim/_pyrtl.py
@@ -138,7 +138,7 @@ class _RHSValueCompiler(_ValueCompiler):
         if len(value.operands) == 1:
             arg, = value.operands
             if value.operator == "~":
-                return f"(~{self(arg)})"
+                return f"(~{mask(arg)})"
             if value.operator == "-":
                 return f"(-{sign(arg)})"
             if value.operator == "b":
diff --git a/tests/test_sim.py b/tests/test_sim.py
index b5acb45..6d38197 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -1,4 +1,5 @@
 import os
+import warnings
 from contextlib import contextmanager
 
 from amaranth._utils import flatten
@@ -872,6 +873,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                 with sim.write_vcd(f):
                     pass
 
+    def test_no_negated_boolean_warning(self):
+        m = Module()
+        a = Signal()
+        b = Signal()
+        m.d.comb += a.eq(~(b == b))
+        with warnings.catch_warnings(record=True) as warns:
+            Simulator(m).run()
+            self.assertEqual(warns, [])
+
 
 class SimulatorRegressionTestCase(FHDLTestCase):
     def test_bug_325(self):