From 4ec9cbbffe80985f791ce22f8c328520ee7bd0d6 Mon Sep 17 00:00:00 2001 From: Charlotte Date: Fri, 23 Jun 2023 00:16:29 +1000 Subject: [PATCH] sim._pyrtl: py3.12+: convert to int before bitwise negating. Amaranth bitwise negation `~` compiles to Python bitwise negation `~` in simulation; the same holds for comparison operators such as `==`. Thus an expression such as `~(a == b)` in simulation will compile to Python that takes the bitwise negation of the comparison result, which will be an actual bool. On 3.12, the result is a `DeprecationWarning` emitted only at simulation run-time. When negating in simulation, coerce the value to an int. `mask` is sufficient as we do no further arithmetic here. --- amaranth/sim/_pyrtl.py | 2 +- tests/test_sim.py | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/amaranth/sim/_pyrtl.py b/amaranth/sim/_pyrtl.py index fb18298..1545686 100644 --- a/amaranth/sim/_pyrtl.py +++ b/amaranth/sim/_pyrtl.py @@ -138,7 +138,7 @@ class _RHSValueCompiler(_ValueCompiler): if len(value.operands) == 1: arg, = value.operands if value.operator == "~": - return f"(~{self(arg)})" + return f"(~{mask(arg)})" if value.operator == "-": return f"(-{sign(arg)})" if value.operator == "b": diff --git a/tests/test_sim.py b/tests/test_sim.py index b5acb45..6d38197 100644 --- a/tests/test_sim.py +++ b/tests/test_sim.py @@ -1,4 +1,5 @@ import os +import warnings from contextlib import contextmanager from amaranth._utils import flatten @@ -872,6 +873,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase): with sim.write_vcd(f): pass + def test_no_negated_boolean_warning(self): + m = Module() + a = Signal() + b = Signal() + m.d.comb += a.eq(~(b == b)) + with warnings.catch_warnings(record=True) as warns: + Simulator(m).run() + self.assertEqual(warns, []) + class SimulatorRegressionTestCase(FHDLTestCase): def test_bug_325(self):