From 4f6b0f23c2820b41dc9cb0c8c9f539e8b2d3a745 Mon Sep 17 00:00:00 2001
From: Wanda <wanda@phinode.net>
Date: Wed, 10 Apr 2024 01:52:14 +0200
Subject: [PATCH] vendor.{_gowin,_lattice_*}: fix DDR buffer naming.

---
 amaranth/vendor/_gowin.py               | 4 ++--
 amaranth/vendor/_lattice_ecp5.py        | 4 ++--
 amaranth/vendor/_lattice_machxo_2_3l.py | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/amaranth/vendor/_gowin.py b/amaranth/vendor/_gowin.py
index 430de9b..17d7d73 100644
--- a/amaranth/vendor/_gowin.py
+++ b/amaranth/vendor/_gowin.py
@@ -134,7 +134,7 @@ class DDRBuffer(io.DDRBuffer):
             i0_inv = Signal(len(self.port))
             i1_inv = Signal(len(self.port))
             for bit in range(len(self.port)):
-                m.submodules.i_ddr = Instance("IDDR",
+                m.submodules[f"i_ddr{bit}"] = Instance("IDDR",
                     i_CLK=ClockSignal(self.i_domain),
                     i_D=buf.i[bit],
                     o_Q0=i0_inv[bit],
@@ -147,7 +147,7 @@ class DDRBuffer(io.DDRBuffer):
             o0_inv = self.o[0] ^ inv_mask
             o1_inv = self.o[1] ^ inv_mask
             for bit in range(len(self.port)):
-                m.submodules.o_ddr = Instance("ODDR",
+                m.submodules[f"o_ddr{bit}"] = Instance("ODDR",
                     p_TXCLK_POL=0, # default -> Q1 changes on posedge of CLK
                     i_CLK=ClockSignal(self.o_domain),
                     i_D0=o0_inv[bit],
diff --git a/amaranth/vendor/_lattice_ecp5.py b/amaranth/vendor/_lattice_ecp5.py
index 6136490..ba4c4eb 100644
--- a/amaranth/vendor/_lattice_ecp5.py
+++ b/amaranth/vendor/_lattice_ecp5.py
@@ -134,7 +134,7 @@ class DDRBuffer(io.DDRBuffer):
             i0_inv = Signal(len(self.port))
             i1_inv = Signal(len(self.port))
             for bit in range(len(self.port)):
-                m.submodules.i_ddr = Instance("IDDRX1F",
+                m.submodules[f"i_ddr{bit}"] = Instance("IDDRX1F",
                     i_SCLK=ClockSignal(self.i_domain),
                     i_RST=Const(0),
                     i_D=buf.i[bit],
@@ -152,7 +152,7 @@ class DDRBuffer(io.DDRBuffer):
                 o1_inv.eq(self.o[1] ^ inv_mask),
             ]
             for bit in range(len(self.port)):
-                m.submodules.o_ddr = Instance("ODDRX1F",
+                m.submodules[f"o_ddr{bit}"] = Instance("ODDRX1F",
                     i_SCLK=ClockSignal(self.o_domain),
                     i_RST=Const(0),
                     i_D0=o0_inv[bit],
diff --git a/amaranth/vendor/_lattice_machxo_2_3l.py b/amaranth/vendor/_lattice_machxo_2_3l.py
index d137138..b36262b 100644
--- a/amaranth/vendor/_lattice_machxo_2_3l.py
+++ b/amaranth/vendor/_lattice_machxo_2_3l.py
@@ -21,7 +21,7 @@ class DDRBuffer(io.DDRBuffer):
             i0_inv = Signal(len(self.port))
             i1_inv = Signal(len(self.port))
             for bit in range(len(self.port)):
-                m.submodules.i_ddr = Instance("IDDRXE",
+                m.submodules[f"i_ddr{bit}"] = Instance("IDDRXE",
                     i_SCLK=ClockSignal(self.i_domain),
                     i_RST=Const(0),
                     i_D=buf.i[bit],
@@ -39,7 +39,7 @@ class DDRBuffer(io.DDRBuffer):
                 o1_inv.eq(self.o[1] ^ inv_mask),
             ]
             for bit in range(len(self.port)):
-                m.submodules.o_ddr = Instance("ODDRXE",
+                m.submodules[f"o_ddr{bit}"] = Instance("ODDRXE",
                     i_SCLK=ClockSignal(self.o_domain),
                     i_RST=Const(0),
                     i_D0=o0_inv[bit],