From 59a83cf7ebce6594dacaf74ad11fa8ab201893ff Mon Sep 17 00:00:00 2001 From: Charlotte Date: Sat, 24 Jun 2023 13:18:53 +1000 Subject: [PATCH] test_sim: add failing test case for bitwise binary ops. See https://github.com/amaranth-lang/amaranth/pull/826#event-9609577585. --- tests/test_sim.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tests/test_sim.py b/tests/test_sim.py index 6d38197..0cc8f50 100644 --- a/tests/test_sim.py +++ b/tests/test_sim.py @@ -927,3 +927,12 @@ class SimulatorRegressionTestCase(FHDLTestCase): r"^Adding a clock process that drives a clock domain object named 'sync', " r"which is distinct from an identically named domain in the simulated design$"): sim.add_clock(1e-6, domain=ClockDomain("sync")) + + def test_bug_826(self): + sim = Simulator(Module()) + def process(): + self.assertEqual((yield C(0b0000, 4) | ~C(1, 1)), 0b0000) + self.assertEqual((yield C(0b1111, 4) & ~C(1, 1)), 0b0000) + self.assertEqual((yield C(0b1111, 4) ^ ~C(1, 1)), 0b1111) + sim.add_process(process) + sim.run()