diff --git a/amaranth/asserts.py b/amaranth/asserts.py
index 6ff2037..e7701ba 100644
--- a/amaranth/asserts.py
+++ b/amaranth/asserts.py
@@ -1,4 +1,4 @@
-from .hdl.ast import AnyConst, AnySeq, Initial, Assert, Assume, Cover
+from .hdl._ast import AnyConst, AnySeq, Initial, Assert, Assume, Cover
 
 
 __all__ = ["AnyConst", "AnySeq", "Initial", "Assert", "Assume", "Cover"]
diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py
index f884be5..3c5ffcf 100644
--- a/amaranth/back/rtlil.py
+++ b/amaranth/back/rtlil.py
@@ -6,7 +6,7 @@ import re
 
 from .._utils import flatten
 from ..utils import bits_for
-from ..hdl import ast, ir, mem, xfrm, _repr
+from ..hdl import _ast, _ir, _mem, _xfrm, _repr
 from ..lib import wiring
 
 
@@ -27,7 +27,7 @@ def _signed(value):
         return False
     elif isinstance(value, int):
         return value < 0
-    elif isinstance(value, ast.Const):
+    elif isinstance(value, _ast.Const):
         return value.signed
     else:
         assert False, f"Invalid constant {value!r}"
@@ -43,8 +43,8 @@ def _const(value):
             # This code path is only used for Instances, where Verilog-like behavior is desirable.
             # Verilog ensures that integers with unspecified width are 32 bits wide or more.
             width = max(32, bits_for(value))
-            return _const(ast.Const(value, width))
-    elif isinstance(value, ast.Const):
+            return _const(_ast.Const(value, width))
+    elif isinstance(value, _ast.Const):
         value_twos_compl = value.value & ((1 << value.width) - 1)
         return "{}'{:0{}b}".format(value.width, value_twos_compl, value.width)
     else:
@@ -301,12 +301,12 @@ class _LegalizeValue(Exception):
 class _ValueCompilerState:
     def __init__(self, rtlil):
         self.rtlil  = rtlil
-        self.wires  = ast.SignalDict()
-        self.driven = ast.SignalDict()
-        self.ports  = ast.SignalDict()
-        self.anys   = ast.ValueDict()
+        self.wires  = _ast.SignalDict()
+        self.driven = _ast.SignalDict()
+        self.ports  = _ast.SignalDict()
+        self.anys   = _ast.ValueDict()
 
-        self.expansions = ast.ValueDict()
+        self.expansions = _ast.ValueDict()
 
     def add_driven(self, signal, sync):
         self.driven[signal] = sync
@@ -350,7 +350,7 @@ class _ValueCompilerState:
         # For every signal in the sync domain, assign \sig's initial value (using the \init reg
         # attribute) to the reset value.
         if is_sync_driven:
-            attrs["init"] = ast.Const(signal.reset, signal.width)
+            attrs["init"] = _ast.Const(signal.reset, signal.width)
 
         wire_curr = self.rtlil.wire(width=signal.width, name=wire_name,
                                     port_id=port_id, port_kind=port_kind,
@@ -383,7 +383,7 @@ class _ValueCompilerState:
             del self.expansions[value]
 
 
-class _ValueCompiler(xfrm.ValueVisitor):
+class _ValueCompiler(_xfrm.ValueVisitor):
     def __init__(self, state):
         self.s = state
 
@@ -419,7 +419,7 @@ class _ValueCompiler(xfrm.ValueVisitor):
 
     def on_ArrayProxy(self, value):
         index = self.s.expand(value.index)
-        if isinstance(index, ast.Const):
+        if isinstance(index, _ast.Const):
             if index.value < len(value.elems):
                 elem = value.elems[index.value]
             else:
@@ -523,12 +523,12 @@ class _RHSValueCompiler(_ValueCompiler):
         return res
 
     def match_shape(self, value, new_shape):
-        if isinstance(value, ast.Const):
-            return self(ast.Const(value.value, new_shape))
+        if isinstance(value, _ast.Const):
+            return self(_ast.Const(value.value, new_shape))
 
         value_shape = value.shape()
         if new_shape.width <= value_shape.width:
-            return self(ast.Slice(value, 0, new_shape.width))
+            return self(_ast.Slice(value, 0, new_shape.width))
 
         res = self.s.rtlil.wire(width=new_shape.width, src=_src(value.src_loc))
         self.s.rtlil.cell("$pos", ports={
@@ -548,7 +548,7 @@ class _RHSValueCompiler(_ValueCompiler):
             lhs_wire = self(lhs)
             rhs_wire = self(rhs)
         else:
-            lhs_shape = rhs_shape = ast.signed(max(lhs_shape.width + rhs_shape.signed,
+            lhs_shape = rhs_shape = _ast.signed(max(lhs_shape.width + rhs_shape.signed,
                                                    rhs_shape.width + lhs_shape.signed))
             lhs_wire = self.match_shape(lhs, lhs_shape)
             rhs_wire = self.match_shape(rhs, rhs_shape)
@@ -570,7 +570,7 @@ class _RHSValueCompiler(_ValueCompiler):
             res = self.s.rtlil.wire(width=res_shape.width, src=_src(value.src_loc))
             self.s.rtlil.cell("$mux", ports={
                 "\\A": divmod_res,
-                "\\B": self(ast.Const(0, res_shape)),
+                "\\B": self(_ast.Const(0, res_shape)),
                 "\\S": self(rhs == 0),
                 "\\Y": res,
             }, params={
@@ -608,7 +608,7 @@ class _RHSValueCompiler(_ValueCompiler):
             raise TypeError # :nocov:
 
     def _prepare_value_for_Slice(self, value):
-        if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
+        if isinstance(value, (_ast.Signal, _ast.Slice, _ast.Cat)):
             sigspec = self(value)
         else:
             sigspec = self.s.rtlil.wire(len(value), src=_src(value.src_loc))
@@ -664,7 +664,7 @@ class _LHSValueCompiler(_ValueCompiler):
         if new_shape.width == value_shape.width:
             return self(value)
         elif new_shape.width < value_shape.width:
-            return self(ast.Slice(value, 0, new_shape.width))
+            return self(_ast.Slice(value, 0, new_shape.width))
         else: # new_shape.width > value_shape.width
             dummy_bits = new_shape.width - value_shape.width
             dummy_wire = self.s.rtlil.wire(dummy_bits)
@@ -677,15 +677,15 @@ class _LHSValueCompiler(_ValueCompiler):
         return wire_next or wire_curr
 
     def _prepare_value_for_Slice(self, value):
-        assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat, ast.Part))
+        assert isinstance(value, (_ast.Signal, _ast.Slice, _ast.Cat, _ast.Part))
         return self(value)
 
     def on_Part(self, value):
         offset = self.s.expand(value.offset)
-        if isinstance(offset, ast.Const):
+        if isinstance(offset, _ast.Const):
             start = offset.value * value.stride
             stop  = start + value.width
-            slice = self(ast.Slice(value.value, start, min(len(value.value), stop)))
+            slice = self(_ast.Slice(value.value, start, min(len(value.value), stop)))
             if len(value.value) >= stop:
                 return slice
             else:
@@ -701,7 +701,7 @@ class _LHSValueCompiler(_ValueCompiler):
                                  value.src_loc)
 
 
-class _StatementCompiler(xfrm.StatementVisitor):
+class _StatementCompiler(_xfrm.StatementVisitor):
     def __init__(self, state, rhs_compiler, lhs_compiler):
         self.state        = state
         self.rhs_compiler = rhs_compiler
@@ -780,7 +780,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
                 case_src = None
                 if values in stmt.case_src_locs:
                     case_src = _src(stmt.case_src_locs[values])
-                if isinstance(stmt.test, ast.Signal) and stmt.test.decoder:
+                if isinstance(stmt.test, _ast.Signal) and stmt.test.decoder:
                     decoded_values = []
                     for value in values:
                         if "-" in value:
@@ -806,7 +806,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
                 for branch, test in zip(legalize.branches, tests):
                     with self.case(switch, (test,)):
                         self._wrap_assign = False
-                        branch_value = ast.Const(branch, shape)
+                        branch_value = _ast.Const(branch, shape)
                         with self.state.expand_to(legalize.value, branch_value):
                             self.on_statement(stmt)
             self._wrap_assign = True
@@ -817,7 +817,7 @@ class _StatementCompiler(xfrm.StatementVisitor):
 
 
 def _convert_fragment(builder, fragment, name_map, hierarchy):
-    if isinstance(fragment, ir.Instance):
+    if isinstance(fragment, _ir.Instance):
         port_map = OrderedDict()
         for port_name, (value, dir) in fragment.named_ports.items():
             port_map[f"\\{port_name}"] = value
@@ -829,10 +829,10 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
         else:
             return f"\\{fragment.type}", port_map, params
 
-    if isinstance(fragment, mem.MemoryInstance):
+    if isinstance(fragment, _mem.MemoryInstance):
         memory = fragment.memory
-        init = "".join(format(ast.Const(elem, ast.unsigned(memory.width)).value, f"0{memory.width}b") for elem in reversed(memory.init))
-        init = ast.Const(int(init or "0", 2), memory.depth * memory.width)
+        init = "".join(format(_ast.Const(elem, _ast.unsigned(memory.width)).value, f"0{memory.width}b") for elem in reversed(memory.init))
+        init = _ast.Const(int(init or "0", 2), memory.depth * memory.width)
         rd_clk = []
         rd_clk_enable = 0
         rd_clk_polarity = 0
@@ -849,7 +849,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                         if port.domain == write_port.domain:
                             rd_transparency_mask |= 1 << (index * len(fragment.write_ports) + write_index)
             else:
-                rd_clk.append(ast.Const(0, 1))
+                rd_clk.append(_ast.Const(0, 1))
         wr_clk = []
         wr_clk_enable = 0
         wr_clk_polarity = 0
@@ -863,36 +863,36 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
             "MEMID": builder._make_name(hierarchy[-1], local=False),
             "SIZE": memory.depth,
             "OFFSET": 0,
-            "ABITS": ast.Shape.cast(range(memory.depth)).width,
+            "ABITS": _ast.Shape.cast(range(memory.depth)).width,
             "WIDTH": memory.width,
             "INIT": init,
             "RD_PORTS": len(fragment.read_ports),
-            "RD_CLK_ENABLE": ast.Const(rd_clk_enable, max(1, len(fragment.read_ports))),
-            "RD_CLK_POLARITY": ast.Const(rd_clk_polarity, max(1, len(fragment.read_ports))),
-            "RD_TRANSPARENCY_MASK": ast.Const(rd_transparency_mask, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
-            "RD_COLLISION_X_MASK": ast.Const(0, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
-            "RD_WIDE_CONTINUATION": ast.Const(0, max(1, len(fragment.read_ports))),
-            "RD_CE_OVER_SRST": ast.Const(0, max(1, len(fragment.read_ports))),
-            "RD_ARST_VALUE": ast.Const(0, len(fragment.read_ports) * memory.width),
-            "RD_SRST_VALUE": ast.Const(0, len(fragment.read_ports) * memory.width),
-            "RD_INIT_VALUE": ast.Const(0, len(fragment.read_ports) * memory.width),
+            "RD_CLK_ENABLE": _ast.Const(rd_clk_enable, max(1, len(fragment.read_ports))),
+            "RD_CLK_POLARITY": _ast.Const(rd_clk_polarity, max(1, len(fragment.read_ports))),
+            "RD_TRANSPARENCY_MASK": _ast.Const(rd_transparency_mask, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
+            "RD_COLLISION_X_MASK": _ast.Const(0, max(1, len(fragment.read_ports) * len(fragment.write_ports))),
+            "RD_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment.read_ports))),
+            "RD_CE_OVER_SRST": _ast.Const(0, max(1, len(fragment.read_ports))),
+            "RD_ARST_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
+            "RD_SRST_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
+            "RD_INIT_VALUE": _ast.Const(0, len(fragment.read_ports) * memory.width),
             "WR_PORTS": len(fragment.write_ports),
-            "WR_CLK_ENABLE": ast.Const(wr_clk_enable, max(1, len(fragment.write_ports))),
-            "WR_CLK_POLARITY": ast.Const(wr_clk_polarity, max(1, len(fragment.write_ports))),
-            "WR_PRIORITY_MASK": ast.Const(0, max(1, len(fragment.write_ports) * len(fragment.write_ports))),
-            "WR_WIDE_CONTINUATION": ast.Const(0, max(1, len(fragment.write_ports))),
+            "WR_CLK_ENABLE": _ast.Const(wr_clk_enable, max(1, len(fragment.write_ports))),
+            "WR_CLK_POLARITY": _ast.Const(wr_clk_polarity, max(1, len(fragment.write_ports))),
+            "WR_PRIORITY_MASK": _ast.Const(0, max(1, len(fragment.write_ports) * len(fragment.write_ports))),
+            "WR_WIDE_CONTINUATION": _ast.Const(0, max(1, len(fragment.write_ports))),
         }
         port_map = {
-            "\\RD_CLK": ast.Cat(rd_clk),
-            "\\RD_EN": ast.Cat(port.en for port in fragment.read_ports),
-            "\\RD_ARST": ast.Const(0, len(fragment.read_ports)),
-            "\\RD_SRST": ast.Const(0, len(fragment.read_ports)),
-            "\\RD_ADDR": ast.Cat(port.addr for port in fragment.read_ports),
-            "\\RD_DATA": ast.Cat(port.data for port in fragment.read_ports),
-            "\\WR_CLK": ast.Cat(wr_clk),
-            "\\WR_EN": ast.Cat(ast.Cat(en_bit.replicate(port.granularity) for en_bit in port.en) for port in fragment.write_ports),
-            "\\WR_ADDR": ast.Cat(port.addr for port in fragment.write_ports),
-            "\\WR_DATA": ast.Cat(port.data for port in fragment.write_ports),
+            "\\RD_CLK": _ast.Cat(rd_clk),
+            "\\RD_EN": _ast.Cat(port.en for port in fragment.read_ports),
+            "\\RD_ARST": _ast.Const(0, len(fragment.read_ports)),
+            "\\RD_SRST": _ast.Const(0, len(fragment.read_ports)),
+            "\\RD_ADDR": _ast.Cat(port.addr for port in fragment.read_ports),
+            "\\RD_DATA": _ast.Cat(port.data for port in fragment.read_ports),
+            "\\WR_CLK": _ast.Cat(wr_clk),
+            "\\WR_EN": _ast.Cat(_ast.Cat(en_bit.replicate(port.granularity) for en_bit in port.en) for port in fragment.write_ports),
+            "\\WR_ADDR": _ast.Cat(port.addr for port in fragment.write_ports),
+            "\\WR_DATA": _ast.Cat(port.data for port in fragment.write_ports),
         }
         return "$mem_v2", port_map, params
 
@@ -931,7 +931,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
         # name) names.
         for subfragment, sub_name in fragment.subfragments:
             if not (subfragment.ports or subfragment.statements or subfragment.subfragments or
-                    isinstance(subfragment, (ir.Instance, mem.MemoryInstance))):
+                    isinstance(subfragment, (_ir.Instance, _mem.MemoryInstance))):
                 # If the fragment is completely empty, skip translating it, otherwise synthesis
                 # tools (including Yosys and Vivado) will treat it as a black box when it is
                 # loaded after conversion to Verilog.
@@ -946,15 +946,15 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
 
             sub_ports = OrderedDict()
             for port, value in sub_port_map.items():
-                if not isinstance(subfragment, (ir.Instance, mem.MemoryInstance)):
+                if not isinstance(subfragment, (_ir.Instance, _mem.MemoryInstance)):
                     for signal in value._rhs_signals():
                         compiler_state.resolve_curr(signal, prefix=sub_name)
                 if len(value) > 0 or sub_type == "$mem_v2":
                     sub_ports[port] = rhs_compiler(value)
 
-            if isinstance(subfragment, ir.Instance):
+            if isinstance(subfragment, _ir.Instance):
                 src = _src(subfragment.src_loc)
-            elif isinstance(subfragment, mem.MemoryInstance):
+            elif isinstance(subfragment, _mem.MemoryInstance):
                 src = _src(subfragment.memory.src_loc)
             else:
                 src = ""
@@ -969,11 +969,11 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
         # Therefore, we translate the fragment as many times as there are independent groups
         # of signals (a group is a transitive closure of signals that appear together on LHS),
         # splitting them into many RTLIL (and thus Verilog) processes.
-        lhs_grouper = xfrm.LHSGroupAnalyzer()
+        lhs_grouper = _xfrm.LHSGroupAnalyzer()
         lhs_grouper.on_statements(fragment.statements)
 
         for group, group_signals in lhs_grouper.groups().items():
-            lhs_group_filter = xfrm.LHSGroupFilter(group_signals)
+            lhs_group_filter = _xfrm.LHSGroupFilter(group_signals)
             group_stmts = lhs_group_filter(fragment.statements)
 
             with module.process(name=f"$group_{group}") as process:
@@ -985,7 +985,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                         if signal not in group_signals:
                             continue
                         if domain is None:
-                            prev_value = ast.Const(signal.reset, signal.width)
+                            prev_value = _ast.Const(signal.reset, signal.width)
                         else:
                             prev_value = signal
                         case.assign(lhs_compiler(signal), rhs_compiler(prev_value))
@@ -1026,8 +1026,8 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                     "\\D": wire_next,
                     "\\Q": wire_curr
                 }, params={
-                    "ARST_POLARITY": ast.Const(1),
-                    "ARST_VALUE": ast.Const(signal.reset, signal.width),
+                    "ARST_POLARITY": _ast.Const(1),
+                    "ARST_VALUE": _ast.Const(signal.reset, signal.width),
                     "CLK_POLARITY": int(cd.clk_edge == "pos"),
                     "WIDTH": signal.width
                 })
@@ -1041,7 +1041,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
         # alternatives are to add ports for undriven signals (which requires choosing one module
         # to drive it to reset value arbitrarily) or to replace them with their reset value (which
         # removes valuable source location information).
-        driven = ast.SignalSet()
+        driven = _ast.SignalSet()
         for domain, signals in fragment.iter_drivers():
             driven.update(flatten(signal._lhs_signals() for signal in signals))
         driven.update(fragment.iter_ports(dir="i"))
@@ -1054,7 +1054,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
             if wire in driven:
                 continue
             wire_curr, _ = compiler_state.wires[wire]
-            module.connect(wire_curr, rhs_compiler(ast.Const(wire.reset, wire.width)))
+            module.connect(wire_curr, rhs_compiler(_ast.Const(wire.reset, wire.width)))
 
     # Collect the names we've given to our ports in RTLIL, and correlate these with the signals
     # represented by these ports. If we are a submodule, this will be necessary to create a cell
@@ -1075,9 +1075,9 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
 
 
 def convert_fragment(fragment, name="top", *, emit_src=True):
-    assert isinstance(fragment, ir.Fragment)
+    assert isinstance(fragment, _ir.Fragment)
     builder = _Builder(emit_src=emit_src)
-    name_map = ast.SignalDict()
+    name_map = _ast.SignalDict()
     _convert_fragment(builder, fragment, name_map, hierarchy=(name,))
     return str(builder), name_map
 
@@ -1088,12 +1088,12 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
             isinstance(elaboratable.signature, wiring.Signature)):
         ports = []
         for path, member, value in elaboratable.signature.flatten(elaboratable):
-            if isinstance(value, ast.ValueCastable):
+            if isinstance(value, _ast.ValueCastable):
                 value = value.as_value()
-            if isinstance(value, ast.Value):
+            if isinstance(value, _ast.Value):
                 ports.append(value)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
-    fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
+    fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     il_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
     return il_text
diff --git a/amaranth/back/verilog.py b/amaranth/back/verilog.py
index ff688eb..d5c75a1 100644
--- a/amaranth/back/verilog.py
+++ b/amaranth/back/verilog.py
@@ -1,5 +1,5 @@
 from .._toolchain.yosys import *
-from ..hdl import ast, ir
+from ..hdl import _ast, _ir
 from ..lib import wiring
 from . import rtlil
 
@@ -49,12 +49,12 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
             isinstance(elaboratable.signature, wiring.Signature)):
         ports = []
         for path, member, value in elaboratable.signature.flatten(elaboratable):
-            if isinstance(value, ast.ValueCastable):
+            if isinstance(value, _ast.ValueCastable):
                 value = value.as_value()
-            if isinstance(value, ast.Value):
+            if isinstance(value, _ast.Value):
                 ports.append(value)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
-    fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
+    fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)
     return verilog_text
diff --git a/amaranth/build/plat.py b/amaranth/build/plat.py
index 309099d..aee7beb 100644
--- a/amaranth/build/plat.py
+++ b/amaranth/build/plat.py
@@ -9,7 +9,7 @@ import jinja2
 from .. import __version__
 from .._toolchain import *
 from ..hdl import *
-from ..hdl.xfrm import DomainLowerer
+from ..hdl._xfrm import DomainLowerer
 from ..lib.cdc import ResetSynchronizer
 from ..back import rtlil, verilog
 from .res import *
diff --git a/amaranth/build/res.py b/amaranth/build/res.py
index f7cdec1..e5be84b 100644
--- a/amaranth/build/res.py
+++ b/amaranth/build/res.py
@@ -1,7 +1,7 @@
 from collections import OrderedDict
 import warnings
 
-from ..hdl.ast import *
+from ..hdl._ast import *
 with warnings.catch_warnings():
     warnings.filterwarnings(action="ignore", category=DeprecationWarning)
     from ..hdl.rec import *
diff --git a/amaranth/cli.py b/amaranth/cli.py
index 56f4e74..87ff10e 100644
--- a/amaranth/cli.py
+++ b/amaranth/cli.py
@@ -1,6 +1,6 @@
 import argparse
 
-from .hdl.ir import Fragment
+from .hdl._ir import Fragment
 from .back import rtlil, cxxrtl, verilog
 from .sim import Simulator
 
diff --git a/amaranth/hdl/__init__.py b/amaranth/hdl/__init__.py
index 1e506d0..e9fdb85 100644
--- a/amaranth/hdl/__init__.py
+++ b/amaranth/hdl/__init__.py
@@ -1,24 +1,29 @@
-import warnings
-
-from .ast import Shape, unsigned, signed
-from .ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
-from .dsl import Module
-from .cd import ClockDomain
-from .ir import Elaboratable, Fragment, Instance
-from .mem import Memory
-with warnings.catch_warnings():
-    warnings.filterwarnings(action="ignore", category=DeprecationWarning)
-    from .rec import Record
-from .xfrm import DomainRenamer, ResetInserter, EnableInserter
+from ._ast import Shape, unsigned, signed, ShapeCastable, ShapeLike
+from ._ast import Value, ValueCastable, ValueLike
+from ._ast import Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
+from ._dsl import SyntaxError, SyntaxWarning, Module
+from ._cd import DomainError, ClockDomain
+from ._ir import UnusedElaboratable, Elaboratable, DriverConflict, Fragment, Instance
+from ._mem import Memory, ReadPort, WritePort, DummyPort
+from ._rec import Record
+from ._xfrm import DomainRenamer, ResetInserter, EnableInserter
 
 
 __all__ = [
-    "Shape", "unsigned", "signed",
-    "Value", "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
-    "Module",
-    "ClockDomain",
-    "Elaboratable", "Fragment", "Instance",
-    "Memory",
+    # _ast
+    "Shape", "unsigned", "signed", "ShapeCastable", "ShapeLike",
+    "Value", "ValueCastable", "ValueLike",
+    "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
+    # _dsl
+    "SyntaxError", "SyntaxWarning", "Module",
+    # _cd
+    "DomainError", "ClockDomain",
+    # _ir
+    "UnusedElaboratable", "Elaboratable", "DriverConflict", "Fragment", "Instance",
+    # _mem
+    "Memory", "ReadPort", "WritePort", "DummyPort",
+    # _rec
     "Record",
+    # _xfrm
     "DomainRenamer", "ResetInserter", "EnableInserter",
 ]
diff --git a/amaranth/hdl/_cd.py b/amaranth/hdl/_cd.py
index 33212d9..683315e 100644
--- a/amaranth/hdl/_cd.py
+++ b/amaranth/hdl/_cd.py
@@ -1,5 +1,5 @@
 from .. import tracer
-from .ast import Signal
+from ._ast import Signal
 
 
 __all__ = ["ClockDomain", "DomainError"]
diff --git a/amaranth/hdl/_dsl.py b/amaranth/hdl/_dsl.py
index 5cbfd52..01bb6fa 100644
--- a/amaranth/hdl/_dsl.py
+++ b/amaranth/hdl/_dsl.py
@@ -8,10 +8,10 @@ import sys
 from .._utils import flatten
 from ..utils import bits_for
 from .. import tracer
-from .ast import *
-from .ir import *
-from .cd import *
-from .xfrm import *
+from ._ast import *
+from ._ir import *
+from ._cd import *
+from ._xfrm import *
 
 
 __all__ = ["SyntaxError", "SyntaxWarning", "Module"]
diff --git a/amaranth/hdl/_ir.py b/amaranth/hdl/_ir.py
index 0b7139b..cbdbfed 100644
--- a/amaranth/hdl/_ir.py
+++ b/amaranth/hdl/_ir.py
@@ -6,8 +6,8 @@ import warnings
 from .. import tracer
 from .._utils import *
 from .._unused import *
-from .ast import *
-from .cd import *
+from ._ast import *
+from ._cd import *
 
 
 __all__ = ["UnusedElaboratable", "Elaboratable", "DriverConflict", "Fragment", "Instance"]
@@ -263,7 +263,7 @@ class Fragment:
         return SignalSet(driver_subfrags.keys())
 
     def _propagate_domains_up(self, hierarchy=("top",)):
-        from .xfrm import DomainRenamer
+        from ._xfrm import DomainRenamer
 
         domain_subfrags = defaultdict(set)
 
@@ -327,7 +327,7 @@ class Fragment:
             subfrag._propagate_domains_down()
 
     def _create_missing_domains(self, missing_domain, *, platform=None):
-        from .xfrm import DomainCollector
+        from ._xfrm import DomainCollector
 
         collector = DomainCollector()
         collector(self)
@@ -507,7 +507,7 @@ class Fragment:
                 self.add_ports(sig, dir="i")
 
     def prepare(self, ports=None, missing_domain=lambda name: ClockDomain(name)):
-        from .xfrm import DomainLowerer
+        from ._xfrm import DomainLowerer
 
         new_domains = self._propagate_domains(missing_domain)
         fragment = DomainLowerer()(self)
diff --git a/amaranth/hdl/_mem.py b/amaranth/hdl/_mem.py
index 61b8bc0..a52cec5 100644
--- a/amaranth/hdl/_mem.py
+++ b/amaranth/hdl/_mem.py
@@ -2,8 +2,8 @@ import operator
 from collections import OrderedDict
 
 from .. import tracer
-from .ast import *
-from .ir import Elaboratable, Instance, Fragment
+from ._ast import *
+from ._ir import Elaboratable, Instance, Fragment
 
 
 __all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"]
diff --git a/amaranth/hdl/_rec.py b/amaranth/hdl/_rec.py
index a898143..a02b69b 100644
--- a/amaranth/hdl/_rec.py
+++ b/amaranth/hdl/_rec.py
@@ -6,7 +6,7 @@ from functools import reduce, wraps
 
 from .. import tracer
 from .._utils import union
-from .ast import *
+from ._ast import *
 from ..lib import wiring
 
 
diff --git a/amaranth/hdl/_repr.py b/amaranth/hdl/_repr.py
index adecc87..398d10b 100644
--- a/amaranth/hdl/_repr.py
+++ b/amaranth/hdl/_repr.py
@@ -36,7 +36,7 @@ class FormatCustom(Format):
 
 class Repr:
     def __init__(self, format, value, *, path=()):
-        from .ast import Value # avoid a circular dependency
+        from ._ast import Value # avoid a circular dependency
         assert isinstance(format, Format)
         assert isinstance(value, Value)
         assert isinstance(path, tuple) and all(isinstance(part, (str, int)) for part in path)
diff --git a/amaranth/hdl/_xfrm.py b/amaranth/hdl/_xfrm.py
index 02c6403..900ff46 100644
--- a/amaranth/hdl/_xfrm.py
+++ b/amaranth/hdl/_xfrm.py
@@ -5,11 +5,11 @@ from copy import copy
 
 from .._utils import flatten, _ignore_deprecated
 from .. import tracer
-from .ast import *
-from .ast import _StatementList
-from .cd import *
-from .ir import *
-from .mem import MemoryInstance
+from ._ast import *
+from ._ast import _StatementList
+from ._cd import *
+from ._ir import *
+from ._mem import MemoryInstance
 
 
 __all__ = ["ValueVisitor", "ValueTransformer",
@@ -286,7 +286,7 @@ class FragmentTransformer:
         if isinstance(fragment, MemoryInstance):
             new_fragment = MemoryInstance(fragment.memory, [], [])
             self.map_memory_ports(fragment, new_fragment)
-        elif isinstance(fragment, Instance):            
+        elif isinstance(fragment, Instance):
             new_fragment = Instance(fragment.type, src_loc=fragment.src_loc)
             new_fragment.parameters = OrderedDict(fragment.parameters)
             self.map_named_ports(fragment, new_fragment)
diff --git a/amaranth/lib/data.py b/amaranth/lib/data.py
index e1c35db..1083fa3 100644
--- a/amaranth/lib/data.py
+++ b/amaranth/lib/data.py
@@ -6,7 +6,7 @@ import warnings
 from amaranth._utils import final
 from amaranth.hdl import *
 from amaranth.hdl._repr import *
-from amaranth.hdl.ast import ShapeCastable, ValueCastable
+from amaranth.hdl._ast import ShapeCastable, ValueCastable
 
 
 __all__ = [
diff --git a/amaranth/lib/enum.py b/amaranth/lib/enum.py
index b15d6d5..998d54e 100644
--- a/amaranth/lib/enum.py
+++ b/amaranth/lib/enum.py
@@ -2,7 +2,7 @@ import enum as py_enum
 import warnings
 import operator
 
-from ..hdl.ast import Value, ValueCastable, Shape, ShapeCastable, Const
+from ..hdl._ast import Value, ValueCastable, Shape, ShapeCastable, Const
 from ..hdl._repr import *
 
 
diff --git a/amaranth/lib/wiring.py b/amaranth/lib/wiring.py
index f54c076..d9cb14d 100644
--- a/amaranth/lib/wiring.py
+++ b/amaranth/lib/wiring.py
@@ -4,8 +4,8 @@ import re
 import warnings
 
 from .. import tracer
-from ..hdl.ast import Shape, ShapeCastable, Const, Signal, Value, ValueCastable
-from ..hdl.ir import Elaboratable
+from ..hdl._ast import Shape, ShapeCastable, Const, Signal, Value, ValueCastable
+from ..hdl._ir import Elaboratable
 from .._utils import final
 
 
diff --git a/amaranth/sim/_pycoro.py b/amaranth/sim/_pycoro.py
index e2714a2..e9500c4 100644
--- a/amaranth/sim/_pycoro.py
+++ b/amaranth/sim/_pycoro.py
@@ -1,7 +1,7 @@
 import inspect
 
 from ..hdl import *
-from ..hdl.ast import Statement, SignalSet, ValueCastable
+from ..hdl._ast import Statement, SignalSet, ValueCastable
 from .core import Tick, Settle, Delay, Passive, Active
 from ._base import BaseProcess
 from ._pyrtl import _ValueCompiler, _RHSValueCompiler, _StatementCompiler
diff --git a/amaranth/sim/_pyrtl.py b/amaranth/sim/_pyrtl.py
index bb31cdf..3862593 100644
--- a/amaranth/sim/_pyrtl.py
+++ b/amaranth/sim/_pyrtl.py
@@ -4,8 +4,8 @@ from contextlib import contextmanager
 import sys
 
 from ..hdl import *
-from ..hdl.ast import SignalSet
-from ..hdl.xfrm import ValueVisitor, StatementVisitor, LHSGroupFilter
+from ..hdl._ast import SignalSet
+from ..hdl._xfrm import ValueVisitor, StatementVisitor, LHSGroupFilter
 from ._base import BaseProcess
 
 
diff --git a/amaranth/sim/core.py b/amaranth/sim/core.py
index cd81c8a..64686ce 100644
--- a/amaranth/sim/core.py
+++ b/amaranth/sim/core.py
@@ -2,8 +2,8 @@ import inspect
 import warnings
 
 from .._utils import deprecated
-from ..hdl.cd import *
-from ..hdl.ir import *
+from ..hdl._cd import *
+from ..hdl._ir import *
 from ._base import BaseEngine
 
 
@@ -130,7 +130,7 @@ class Simulator:
         if domain in self._clocked:
             raise ValueError("Domain {!r} already has a clock driving it"
                              .format(domain.name))
-        
+
         # We represent times internally in 1 ps units, but users supply float quantities of seconds
         period = int(period * 1e12)
 
diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py
index 3abfdd5..aac3ab0 100644
--- a/amaranth/sim/pysim.py
+++ b/amaranth/sim/pysim.py
@@ -6,7 +6,7 @@ from vcd.gtkw import GTKWSave
 
 from ..hdl import *
 from ..hdl._repr import *
-from ..hdl.ast import SignalDict, Slice, Operator
+from ..hdl._ast import SignalDict, Slice, Operator
 from ._base import *
 from ._pyrtl import _FragmentCompiler
 from ._pycoro import PyCoroProcess
diff --git a/docs/stdlib/enum.rst b/docs/stdlib/enum.rst
index 2267b60..9887158 100644
--- a/docs/stdlib/enum.rst
+++ b/docs/stdlib/enum.rst
@@ -86,8 +86,8 @@ Like the standard Python :class:`enum.IntEnum` and :class:`enum.IntFlag` classes
 .. doctest::
 
    >>> a = Signal(TransparentEnum)
-   >>> type(a)
-   <class 'amaranth.hdl.ast.Signal'>
+   >>> type(a) is Signal
+   True
 
 It is also possible to define a custom view class for a given enum:
 
diff --git a/tests/test_hdl_ast.py b/tests/test_hdl_ast.py
index 1af21f2..a670f58 100644
--- a/tests/test_hdl_ast.py
+++ b/tests/test_hdl_ast.py
@@ -1,7 +1,7 @@
 import warnings
 from enum import Enum, EnumMeta
 
-from amaranth.hdl.ast import *
+from amaranth.hdl._ast import *
 from amaranth.lib.enum import Enum as AmaranthEnum
 
 from .utils import *
@@ -1024,10 +1024,10 @@ class ArrayTestCase(FHDLTestCase):
             @ValueCastable.lowermethod
             def as_value(self):
                 return Signal()
-            
+
             def shape():
                 return unsigned(1)
-        
+
         a = Array([1,2,3])
         a[MyValue()]
 
diff --git a/tests/test_hdl_cd.py b/tests/test_hdl_cd.py
index 7cb3508..5a9fa73 100644
--- a/tests/test_hdl_cd.py
+++ b/tests/test_hdl_cd.py
@@ -1,4 +1,4 @@
-from amaranth.hdl.cd import *
+from amaranth.hdl._cd import *
 
 from .utils import *
 
diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py
index 06611c3..9914da4 100644
--- a/tests/test_hdl_dsl.py
+++ b/tests/test_hdl_dsl.py
@@ -3,9 +3,9 @@
 import sys
 from collections import OrderedDict
 
-from amaranth.hdl.ast import *
-from amaranth.hdl.cd import *
-from amaranth.hdl.dsl import *
+from amaranth.hdl._ast import *
+from amaranth.hdl._cd import *
+from amaranth.hdl._dsl import *
 from amaranth.lib.enum import Enum
 
 from .utils import *
diff --git a/tests/test_hdl_ir.py b/tests/test_hdl_ir.py
index 7a34727..0b6abc9 100644
--- a/tests/test_hdl_ir.py
+++ b/tests/test_hdl_ir.py
@@ -2,10 +2,10 @@
 
 from collections import OrderedDict
 
-from amaranth.hdl.ast import *
-from amaranth.hdl.cd import *
-from amaranth.hdl.ir import *
-from amaranth.hdl.mem import *
+from amaranth.hdl._ast import *
+from amaranth.hdl._cd import *
+from amaranth.hdl._ir import *
+from amaranth.hdl._mem import *
 
 from .utils import *
 
diff --git a/tests/test_hdl_mem.py b/tests/test_hdl_mem.py
index b371362..4af2e77 100644
--- a/tests/test_hdl_mem.py
+++ b/tests/test_hdl_mem.py
@@ -1,7 +1,7 @@
 # amaranth: UnusedElaboratable=no
 
-from amaranth.hdl.ast import *
-from amaranth.hdl.mem import *
+from amaranth.hdl._ast import *
+from amaranth.hdl._mem import *
 
 from .utils import *
 
diff --git a/tests/test_hdl_rec.py b/tests/test_hdl_rec.py
index 4bf3592..da96b13 100644
--- a/tests/test_hdl_rec.py
+++ b/tests/test_hdl_rec.py
@@ -2,7 +2,7 @@ import warnings
 
 from enum import Enum
 
-from amaranth.hdl.ast import *
+from amaranth.hdl._ast import *
 with warnings.catch_warnings():
     warnings.filterwarnings(action="ignore", category=DeprecationWarning)
     from amaranth.hdl.rec import *
diff --git a/tests/test_hdl_xfrm.py b/tests/test_hdl_xfrm.py
index 8341d2c..1f96589 100644
--- a/tests/test_hdl_xfrm.py
+++ b/tests/test_hdl_xfrm.py
@@ -2,13 +2,13 @@
 
 import warnings
 
-from amaranth.hdl.ast import *
-from amaranth.hdl.cd import *
-from amaranth.hdl.dsl import *
-from amaranth.hdl.ir import *
-from amaranth.hdl.xfrm import *
-from amaranth.hdl.mem import *
-from amaranth.hdl.mem import MemoryInstance
+from amaranth.hdl._ast import *
+from amaranth.hdl._cd import *
+from amaranth.hdl._dsl import *
+from amaranth.hdl._ir import *
+from amaranth.hdl._xfrm import *
+from amaranth.hdl._mem import *
+from amaranth.hdl._mem import MemoryInstance
 
 from .utils import *
 from amaranth._utils import _ignore_deprecated
diff --git a/tests/test_lib_data.py b/tests/test_lib_data.py
index 19b88dc..42f2aca 100644
--- a/tests/test_lib_data.py
+++ b/tests/test_lib_data.py
@@ -3,7 +3,7 @@ import operator
 from unittest import TestCase
 
 from amaranth.hdl import *
-from amaranth.hdl.ast import ShapeCastable
+from amaranth.hdl._ast import ShapeCastable
 from amaranth.lib.data import *
 from amaranth.sim import Simulator
 
diff --git a/tests/test_lib_wiring.py b/tests/test_lib_wiring.py
index 206fa88..26c5076 100644
--- a/tests/test_lib_wiring.py
+++ b/tests/test_lib_wiring.py
@@ -4,7 +4,7 @@ import unittest
 from types import SimpleNamespace as NS
 
 from amaranth import *
-from amaranth.hdl.ast import ValueCastable
+from amaranth.hdl._ast import ValueCastable
 from amaranth.lib import data, enum
 from amaranth.lib.wiring import Flow, In, Out, Member
 from amaranth.lib.wiring import SignatureError, SignatureMembers, FlippedSignatureMembers
diff --git a/tests/test_sim.py b/tests/test_sim.py
index e80c2ef..5614259 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -3,14 +3,14 @@ import warnings
 from contextlib import contextmanager
 
 from amaranth._utils import flatten
-from amaranth.hdl.ast import *
-from amaranth.hdl.cd import  *
-from amaranth.hdl.mem import *
+from amaranth.hdl._ast import *
+from amaranth.hdl._cd import  *
+from amaranth.hdl._mem import *
 with warnings.catch_warnings():
     warnings.filterwarnings(action="ignore", category=DeprecationWarning)
     from amaranth.hdl.rec import *
-from amaranth.hdl.dsl import  *
-from amaranth.hdl.ir import *
+from amaranth.hdl._dsl import  *
+from amaranth.hdl._ir import *
 from amaranth.sim import *
 
 from .utils import *
@@ -695,10 +695,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
             @ValueCastable.lowermethod
             def as_value(self):
                 return Signal()
-            
+
             def shape():
                 return unsigned(1)
-        
+
         a = Array([1,2,3])
         a[MyValue()]
 
diff --git a/tests/test_tracer.py b/tests/test_tracer.py
index 54c6994..fdf82ed 100644
--- a/tests/test_tracer.py
+++ b/tests/test_tracer.py
@@ -1,4 +1,4 @@
-from amaranth.hdl.ast import *
+from amaranth.hdl._ast import *
 from types import SimpleNamespace
 
 from .utils import *
diff --git a/tests/utils.py b/tests/utils.py
index 1f01eb4..a186990 100644
--- a/tests/utils.py
+++ b/tests/utils.py
@@ -6,8 +6,8 @@ import textwrap
 import traceback
 import unittest
 
-from amaranth.hdl.ast import *
-from amaranth.hdl.ir import *
+from amaranth.hdl._ast import *
+from amaranth.hdl._ir import *
 from amaranth.back import rtlil
 from amaranth._toolchain import require_tool