diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 433dd20..0b61268 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -353,7 +353,7 @@ class _RHSValueCompiler(_ValueCompiler):
         if isinstance(value.value, str):
             return "{}'{}".format(value.nbits, value.value)
         else:
-            return "{}'{:b}".format(value.nbits, value.value)
+            return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
 
     def on_Signal(self, value):
         wire_curr, wire_next = self.s.resolve(value)