diff --git a/amaranth/build/plat.py b/amaranth/build/plat.py
index 7a0a13c..432ae67 100644
--- a/amaranth/build/plat.py
+++ b/amaranth/build/plat.py
@@ -34,6 +34,7 @@ class Platform(ResourceManager, metaclass=ABCMeta):
         self.extra_files = OrderedDict()
 
         self._prepared   = False
+        self._design     = None
 
     @property
     def default_clk_constraint(self):
@@ -148,9 +149,16 @@ class Platform(ResourceManager, metaclass=ABCMeta):
             buffer = DomainLowerer()(buffer)
             fragment.add_subfragment(buffer, name=f"pin_{pin.name}")
 
-        ports = [(port.name, port, None) for port in self.iter_ports()]
-        design = Design(fragment, ports, hierarchy=(name,))
-        return self.toolchain_prepare(design, name, **kwargs)
+        self._design = Design(fragment, [], hierarchy=(name,))
+        return self.toolchain_prepare(self._design, name, **kwargs)
+
+    def iter_port_constraints_bits(self):
+        for (name, port, _dir) in self._design.ports:
+            if len(port) == 1:
+                yield name, port.metadata[0].name, port.metadata[0].attrs
+            else:
+                for bit, meta in enumerate(port.metadata):
+                    yield f"{name}[{bit}]", meta.name, meta.attrs
 
     @abstractmethod
     def toolchain_prepare(self, fragment, name, **kwargs):
diff --git a/amaranth/build/res.py b/amaranth/build/res.py
index fe7d0f6..0744ef0 100644
--- a/amaranth/build/res.py
+++ b/amaranth/build/res.py
@@ -107,8 +107,6 @@ class ResourceManager:
         self.connectors = OrderedDict()
         self._conn_pins = OrderedDict()
 
-        # List of all IOPort instances created
-        self._ports     = []
         # List of (pin, port, buffer) pairs for non-dir="-" requests.
         self._pins      = []
         # Constraint list
@@ -220,7 +218,6 @@ class ResourceManager:
                         PortMetadata(name, attrs)
                         for name in phys_names
                     ])
-                    self._ports.append(iop)
                     port = io.SingleEndedPort(iop, invert=phys.invert, direction=direction)
                 if isinstance(phys, DiffPairs):
                     phys_names_p = phys.p.map_names(self._conn_pins, resource)
@@ -234,7 +231,6 @@ class ResourceManager:
                         PortMetadata(name, attrs)
                         for name in phys_names_n
                     ])
-                    self._ports += [p, n]
                     port = io.DifferentialPort(p, n, invert=phys.invert, direction=direction)
 
                 for phys_name in phys_names:
@@ -274,17 +270,6 @@ class ResourceManager:
     def iter_pins(self):
         yield from self._pins
 
-    def iter_ports(self):
-        yield from self._ports
-
-    def iter_port_constraints_bits(self):
-        for port in self._ports:
-            if len(port) == 1:
-                yield port.name, port.metadata[0].name, port.metadata[0].attrs
-            else:
-                for bit, meta in enumerate(port.metadata):
-                    yield f"{port.name}[{bit}]", meta.name, meta.attrs
-
     def add_clock_constraint(self, clock, frequency):
         if isinstance(clock, ClockSignal):
             raise TypeError(f"A clock constraint can only be applied to a Signal, but a "