From 6ce82848d960b368cb226c80e495c2dc5de98172 Mon Sep 17 00:00:00 2001 From: Catherine Date: Fri, 22 Mar 2024 21:19:27 +0000 Subject: [PATCH] =?UTF-8?q?lib.memory:=20`Memory.{r,w}=5Fports`=E2=86=92`.?= =?UTF-8?q?{read,write}=5Fports`.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The abbreviated form was initially added to match `lib.fifo`, but it looks very out of place on `lib.memory`, and we may be moving away from such heavy use of abbreviations anyway. While technically a breaking change, these attributes have very narrow usefulness and so this change qualifies as "minor". --- amaranth/lib/memory.py | 6 ++---- docs/stdlib/memory.rst | 4 ++-- tests/test_lib_memory.py | 12 ++++++------ 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/amaranth/lib/memory.py b/amaranth/lib/memory.py index 697857a..298cb44 100644 --- a/amaranth/lib/memory.py +++ b/amaranth/lib/memory.py @@ -207,18 +207,16 @@ class Memory(wiring.Component): return WritePort(signature, memory=self, domain=domain, src_loc_at=1 + src_loc_at) - # TODO: rename to read_ports @property - def r_ports(self): + def read_ports(self): """All read ports defined so far. This property is provided for the :py:`platform.get_memory()` override. """ return tuple(self._read_ports) - # TODO: rename to write_ports @property - def w_ports(self): + def write_ports(self): """All write ports defined so far. This property is provided for the :py:`platform.get_memory()` override. diff --git a/docs/stdlib/memory.rst b/docs/stdlib/memory.rst index 7331587..2927a2c 100644 --- a/docs/stdlib/memory.rst +++ b/docs/stdlib/memory.rst @@ -131,9 +131,9 @@ Memories .. automethod:: write_port - .. autoproperty:: r_ports + .. autoproperty:: read_ports - .. autoproperty:: w_ports + .. autoproperty:: write_ports Memory ports diff --git a/tests/test_lib_memory.py b/tests/test_lib_memory.py index 07b26c2..91eef93 100644 --- a/tests/test_lib_memory.py +++ b/tests/test_lib_memory.py @@ -121,7 +121,7 @@ class WritePortTestCase(FHDLTestCase): m = memory.Memory(depth=16, shape=8, init=[]) port = memory.WritePort(signature, memory=m, domain="sync") self.assertIs(port.memory, m) - self.assertEqual(m.w_ports, (port,)) + self.assertEqual(m.write_ports, (port,)) signature = memory.WritePort.Signature(shape=MyStruct, addr_width=4) port = signature.create() @@ -228,7 +228,7 @@ class ReadPortTestCase(FHDLTestCase): m = memory.Memory(depth=16, shape=8, init=[]) port = memory.ReadPort(signature, memory=m, domain="sync") self.assertIs(port.memory, m) - self.assertEqual(m.r_ports, (port,)) + self.assertEqual(m.read_ports, (port,)) write_port = m.write_port() port = memory.ReadPort(signature, memory=m, domain="sync", transparent_for=[write_port]) self.assertIs(port.memory, m) @@ -291,8 +291,8 @@ class MemoryTestCase(FHDLTestCase): self.assertEqual(list(m.init), [1, 2, 3, 0]) self.assertEqual(m.init._raw, [1, 2, 3, 0]) self.assertRepr(m.init, "Memory.Init([1, 2, 3, 0], shape=8, depth=4)") - self.assertEqual(m.r_ports, ()) - self.assertEqual(m.w_ports, ()) + self.assertEqual(m.read_ports, ()) + self.assertEqual(m.write_ports, ()) def test_constructor_shapecastable(self): init = [ @@ -375,8 +375,8 @@ class MemoryTestCase(FHDLTestCase): wp = m.write_port() self.assertEqual(wp.signature.addr_width, addr_width) self.assertEqual(wp.signature.shape, 8) - self.assertEqual(m.r_ports, (rp,)) - self.assertEqual(m.w_ports, (wp,)) + self.assertEqual(m.read_ports, (rp,)) + self.assertEqual(m.write_ports, (wp,)) def test_elaborate(self): m = memory.Memory(shape=MyStruct, depth=4, init=[{"a": 1, "b": 2}])