diff --git a/amaranth/sim/_base.py b/amaranth/sim/_base.py
index cf0ca61..49cd9bc 100644
--- a/amaranth/sim/_base.py
+++ b/amaranth/sim/_base.py
@@ -52,10 +52,10 @@ class BaseSimulation:
 
     slots = NotImplemented
 
-    def add_trigger(self, process, signal, *, trigger=None):
+    def add_signal_trigger(self, process, signal, *, trigger=None):
         raise NotImplementedError # :nocov:
 
-    def remove_trigger(self, process, signal):
+    def remove_signal_trigger(self, process, signal):
         raise NotImplementedError # :nocov:
 
     def add_memory_trigger(self, process, memory):
diff --git a/amaranth/sim/_pycoro.py b/amaranth/sim/_pycoro.py
index 8c929b5..63df6ec 100644
--- a/amaranth/sim/_pycoro.py
+++ b/amaranth/sim/_pycoro.py
@@ -42,12 +42,12 @@ class PyCoroProcess(BaseProcess):
         return f"{inspect.getfile(frame)}:{inspect.getlineno(frame)}"
 
     def add_trigger(self, signal, trigger=None):
-        self.state.add_trigger(self, signal, trigger=trigger)
+        self.state.add_signal_trigger(self, signal, trigger=trigger)
         self.waits_on.add(signal)
 
     def clear_triggers(self):
         for signal in self.waits_on:
-            self.state.remove_trigger(self, signal)
+            self.state.remove_signal_trigger(self, signal)
         self.waits_on.clear()
 
     def run(self):
diff --git a/amaranth/sim/_pyrtl.py b/amaranth/sim/_pyrtl.py
index bbf75ea..484d947 100644
--- a/amaranth/sim/_pyrtl.py
+++ b/amaranth/sim/_pyrtl.py
@@ -501,15 +501,15 @@ class _FragmentCompiler:
                         lhs(port._data)(data)
 
                 for input in inputs:
-                    self.state.add_trigger(domain_process, input)
+                    self.state.add_signal_trigger(domain_process, input)
 
             else:
                 domain = fragment.domains[domain_name]
                 clk_trigger = 1 if domain.clk_edge == "pos" else 0
-                self.state.add_trigger(domain_process, domain.clk, trigger=clk_trigger)
+                self.state.add_signal_trigger(domain_process, domain.clk, trigger=clk_trigger)
                 if domain.rst is not None and domain.async_reset:
                     rst_trigger = 1
-                    self.state.add_trigger(domain_process, domain.rst, trigger=rst_trigger)
+                    self.state.add_signal_trigger(domain_process, domain.rst, trigger=rst_trigger)
 
                 for signal in domain_signals:
                     signal_index = self.state.get_signal(signal)
diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py
index 64f86f4..4df2ca7 100644
--- a/amaranth/sim/pysim.py
+++ b/amaranth/sim/pysim.py
@@ -476,13 +476,13 @@ class _PySimulation(BaseSimulation):
             self.memories[memory] = index
             return index
 
-    def add_trigger(self, process, signal, *, trigger=None):
+    def add_signal_trigger(self, process, signal, *, trigger=None):
         index = self.get_signal(signal)
         assert (process not in self.slots[index].waiters or
                 self.slots[index].waiters[process] == trigger)
         self.slots[index].waiters[process] = trigger
 
-    def remove_trigger(self, process, signal):
+    def remove_signal_trigger(self, process, signal):
         index = self.get_signal(signal)
         assert process in self.slots[index].waiters
         del self.slots[index].waiters[process]