From 7cabe350d92373c1b1ed7a3a5e314de1efeda4e2 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Mon, 10 Jun 2024 10:54:09 +0100
Subject: [PATCH] examples: convert to async simulator syntax.

---
 examples/basic/ctr_en.py | 18 +++++++-------
 examples/basic/uart.py   | 51 ++++++++++++++++++++--------------------
 2 files changed, 34 insertions(+), 35 deletions(-)

diff --git a/examples/basic/ctr_en.py b/examples/basic/ctr_en.py
index 7cbd8fd..f695625 100644
--- a/examples/basic/ctr_en.py
+++ b/examples/basic/ctr_en.py
@@ -22,13 +22,13 @@ print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
 
 sim = Simulator(ctr)
 sim.add_clock(1e-6)
-def ce_proc():
-    yield Tick(); yield Tick(); yield Tick()
-    yield ctr.en.eq(1)
-    yield Tick(); yield Tick(); yield Tick()
-    yield ctr.en.eq(0)
-    yield Tick(); yield Tick(); yield Tick()
-    yield ctr.en.eq(1)
-sim.add_testbench(ce_proc)
+async def testbench_ce(ctx):
+    await ctx.tick().repeat(3)
+    ctx.set(ctr.en, 1)
+    await ctx.tick().repeat(3)
+    ctx.set(ctr.en, 0)
+    await ctx.tick().repeat(3)
+    ctx.set(ctr.en,1)
+sim.add_testbench(testbench_ce)
 with sim.write_vcd("ctrl.vcd", "ctrl.gtkw", traces=[ctr.en, ctr.v, ctr.o]):
-    sim.run_until(100e-6, run_passive=True)
+    sim.run_until(100e-6)
diff --git a/examples/basic/uart.py b/examples/basic/uart.py
index 6003e8b..a279bb3 100644
--- a/examples/basic/uart.py
+++ b/examples/basic/uart.py
@@ -110,38 +110,37 @@ if __name__ == "__main__":
         sim = Simulator(uart)
         sim.add_clock(1e-6)
 
-        def loopback_proc():
-            yield Passive()
-            while True:
-                yield uart.rx_i.eq((yield uart.tx_o))
-                yield
-        sim.add_sync_process(loopback_proc)
+        async def testbench_loopback(ctx):
+            async for val in ctx.changed(uart.tx_o):
+                ctx.set(uart.rx_i, val)
 
-        def transmit_proc():
-            assert (yield uart.tx_ack)
-            assert not (yield uart.rx_rdy)
+        sim.add_testbench(testbench_loopback, background=True)
 
-            yield uart.tx_data.eq(0x5A)
-            yield uart.tx_rdy.eq(1)
-            yield
-            yield uart.tx_rdy.eq(0)
-            yield
-            assert not (yield uart.tx_ack)
+        async def testbench_transmit(ctx):
+            assert ctx.get(uart.tx_ack)
+            assert not ctx.get(uart.rx_rdy)
 
-            for _ in range(uart.divisor * 12): yield
+            ctx.set(uart.tx_data, 0x5A)
+            ctx.set(uart.tx_rdy, 1)
+            await ctx.tick()
+            ctx.set(uart.tx_rdy, 0)
+            await ctx.tick()
+            assert not ctx.get(uart.tx_ack)
 
-            assert (yield uart.tx_ack)
-            assert (yield uart.rx_rdy)
-            assert not (yield uart.rx_err)
-            assert (yield uart.rx_data) == 0x5A
+            await ctx.tick().repeat(uart.divisor * 12)
 
-            yield uart.rx_ack.eq(1)
-            yield
-            yield uart.rx_ack.eq(0)
-            yield
-            assert not (yield uart.rx_rdy)
+            assert ctx.get(uart.tx_ack)
+            assert ctx.get(uart.rx_rdy)
+            assert not ctx.get(uart.rx_err)
+            assert ctx.get(uart.rx_data) == 0x5A
 
-        sim.add_sync_process(transmit_proc)
+            ctx.set(uart.rx_ack, 1)
+            await ctx.tick()
+            ctx.set(uart.rx_ack, 0)
+            await ctx.tick()
+            assert not ctx.get(uart.rx_rdy)
+
+        sim.add_testbench(testbench_transmit)
 
         with sim.write_vcd("uart.vcd", "uart.gtkw"):
             sim.run()