diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py
index 388ecb1..6838f37 100644
--- a/amaranth/back/rtlil.py
+++ b/amaranth/back/rtlil.py
@@ -1034,6 +1034,6 @@ def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=Tru
     if ports is None:
         warnings.warn("Implicit port determination is deprecated, specify ports explictly",
                       DeprecationWarning, stacklevel=2)
-    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
+    fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     il_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
     return il_text
diff --git a/amaranth/back/verilog.py b/amaranth/back/verilog.py
index accfddc..62c7192 100644
--- a/amaranth/back/verilog.py
+++ b/amaranth/back/verilog.py
@@ -47,6 +47,6 @@ def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=Tru
     if ports is None:
         warnings.warn("Implicit port determination is deprecated, specify ports explictly",
                       DeprecationWarning, stacklevel=2)
-    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
+    fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src)
     return verilog_text
diff --git a/tests/utils.py b/tests/utils.py
index 1238235..8a5aa77 100644
--- a/tests/utils.py
+++ b/tests/utils.py
@@ -71,7 +71,7 @@ class FHDLTestCase(unittest.TestCase):
             mode=mode,
             depth=depth,
             script=script,
-            rtlil=rtlil.convert(Fragment.get(spec, platform="formal"), ports=())
+            rtlil=rtlil.convert_fragment(Fragment.get(spec, platform="formal").prepare())[0]
         )
         with subprocess.Popen(
                 [require_tool("sby"), "-f", "-d", spec_name],