From 855545b6ff9c33f836812bdcf4d62023d5f48edc Mon Sep 17 00:00:00 2001 From: Catherine Date: Thu, 30 May 2024 10:32:53 +0000 Subject: [PATCH] docs/stdlib/io: minor documentation clarity improvement. --- amaranth/lib/io.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/amaranth/lib/io.py b/amaranth/lib/io.py index 8a1dbe2..e4ea8b2 100644 --- a/amaranth/lib/io.py +++ b/amaranth/lib/io.py @@ -726,10 +726,11 @@ class DDRBuffer(wiring.Component): port : :class:`PortLike` Port driven by the buffer. i_domain : :class:`str` - Name of the input registers' clock domain. Only used when :py:`direction in (Input, Bidir)`. + Name of the input register's clock domain. Used when :py:`direction in (Input, Bidir)`. + Defaults to :py:`"sync"`. o_domain : :class:`str` - Name of the output and output enable registers' clock domain. Only used when - :py:`direction in (Output, Bidir)`. + Name of the output and output enable registers' clock domain. Used when + :py:`direction in (Output, Bidir)`. Defaults to :py:`"sync"`. Attributes ----------