From 8678d5fa14f1baa3ffbaba525bdbe60db5864e72 Mon Sep 17 00:00:00 2001 From: Catherine Date: Tue, 30 Jan 2024 02:49:09 +0000 Subject: [PATCH] hdl.dsl: warn if a case is defined after a default case. --- amaranth/hdl/dsl.py | 6 ++++++ tests/test_hdl_dsl.py | 20 ++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/amaranth/hdl/dsl.py b/amaranth/hdl/dsl.py index 2da0dac..5cbfd52 100644 --- a/amaranth/hdl/dsl.py +++ b/amaranth/hdl/dsl.py @@ -308,6 +308,9 @@ class Module(_ModuleBuilderRoot, Elaboratable): src_loc = tracer.get_src_loc(src_loc_at=1) switch_data = self._get_ctrl("Switch") new_patterns = () + if () in switch_data["cases"]: + warnings.warn("A case defined after the default case will never be active", + SyntaxWarning, stacklevel=3) # This code should accept exactly the same patterns as `v.matches(...)`. for pattern in patterns: if isinstance(pattern, str) and any(bit not in "01- \t" for bit in pattern): @@ -357,6 +360,9 @@ class Module(_ModuleBuilderRoot, Elaboratable): self._check_context("Default", context="Switch") src_loc = tracer.get_src_loc(src_loc_at=1) switch_data = self._get_ctrl("Switch") + if () in switch_data["cases"]: + warnings.warn("A case defined after the default case will never be active", + SyntaxWarning, stacklevel=3) try: _outer_case, self._statements = self._statements, [] self._ctrl_context = None diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py index dddae25..06611c3 100644 --- a/tests/test_hdl_dsl.py +++ b/tests/test_hdl_dsl.py @@ -497,6 +497,26 @@ class DSLTestCase(FHDLTestCase): with m.Case(): pass + def test_Case_after_Default_wrong(self): + m = Module() + with m.Switch(self.w1): + with m.Default(): + pass + with self.assertWarnsRegex(SyntaxWarning, + r"^A case defined after the default case will never be active$"): + with m.Case(): + pass + + def test_Default_after_Default_wrong(self): + m = Module() + with m.Switch(self.w1): + with m.Default(): + pass + with self.assertWarnsRegex(SyntaxWarning, + r"^A case defined after the default case will never be active$"): + with m.Default(): + pass + def test_If_inside_Switch_wrong(self): m = Module() with m.Switch(self.s1):