diff --git a/amaranth/lib/memory.py b/amaranth/lib/memory.py
index a1a69f2..9cd4687 100644
--- a/amaranth/lib/memory.py
+++ b/amaranth/lib/memory.py
@@ -110,6 +110,12 @@ class WritePort:
         def granularity(self):
             return self._granularity
 
+        def __eq__(self, other):
+            return (type(self) is type(other) and
+                    self.addr_width == other.addr_width and
+                    self.shape == other.shape and
+                    self.granularity == other.granularity)
+
         def __repr__(self):
             granularity = f", granularity={self.granularity}" if self.granularity is not None else ""
             return f"WritePort.Signature(addr_width={self.addr_width}, shape={self.shape}{granularity})"
@@ -213,6 +219,11 @@ class ReadPort:
         def shape(self):
             return self._shape
 
+        def __eq__(self, other):
+            return (type(self) is type(other) and
+                    self.addr_width == other.addr_width and
+                    self.shape == other.shape)
+
         def __repr__(self):
             return f"ReadPort.Signature(addr_width={self.addr_width}, shape={self.shape})"
 
diff --git a/tests/test_lib_memory.py b/tests/test_lib_memory.py
index 917097f..eb7512b 100644
--- a/tests/test_lib_memory.py
+++ b/tests/test_lib_memory.py
@@ -83,6 +83,16 @@ class WritePortTestCase(FHDLTestCase):
                 "^Granularity must divide data array length$"):
             WritePort.Signature(addr_width=2, shape=ArrayLayout(8, 8), granularity=3)
 
+    def test_signature_eq(self):
+        sig = WritePort.Signature(addr_width=2, shape=8)
+        self.assertEqual(sig, WritePort.Signature(addr_width=2, shape=8))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=7))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=1, shape=8))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=8, granularity=8))
+        sig = WritePort.Signature(addr_width=2, shape=8, granularity=4)
+        self.assertEqual(sig, WritePort.Signature(addr_width=2, shape=8, granularity=4))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=8, granularity=8))
+
     def test_constructor(self):
         signature = WritePort.Signature(shape=MyStruct, addr_width=4)
         port = WritePort(signature, memory=None, domain="sync")
@@ -171,6 +181,13 @@ class ReadPortTestCase(FHDLTestCase):
                 "^`addr_width` must be a non-negative int, not -2$"):
             ReadPort.Signature(addr_width=-2, shape=8)
 
+    def test_signature_eq(self):
+        sig = ReadPort.Signature(addr_width=2, shape=8)
+        self.assertEqual(sig, ReadPort.Signature(addr_width=2, shape=8))
+        self.assertNotEqual(sig, ReadPort.Signature(addr_width=2, shape=7))
+        self.assertNotEqual(sig, ReadPort.Signature(addr_width=1, shape=8))
+        self.assertNotEqual(sig, WritePort.Signature(addr_width=2, shape=8))
+
     def test_constructor(self):
         signature = ReadPort.Signature(shape=MyStruct, addr_width=4)
         port = ReadPort(signature, memory=None, domain="sync")