diff --git a/amaranth/build/plat.py b/amaranth/build/plat.py index fade608..7a0a13c 100644 --- a/amaranth/build/plat.py +++ b/amaranth/build/plat.py @@ -330,8 +330,15 @@ class TemplatedPlatform(Platform): return f"_{ord(match.group(1)[0]):02x}_" return "".join(escape_one(m) for m in re.finditer(r"([^A-Za-z0-9_])|(.)", string)) - def tcl_quote(string): - return '"' + re.sub(r"([$[\\])", r"\\\1", string) + '"' + def tcl_quote(string, quirk=None): + escaped = '"' + re.sub(r"([$[\\])", r"\\\1", string) + '"' + if quirk == "Diamond": + # Diamond seems to assign `clk\$2` as a name for the Verilog net `\clk$2 `, and + # `clk\\\$2` as a name for the Verilog net `\clk\$2 `. + return escaped.replace("\\", "\\\\") + else: + assert quirk is None + return escaped def verbose(arg): if get_override_flag("verbose"): diff --git a/amaranth/vendor/_lattice.py b/amaranth/vendor/_lattice.py index 9e001c9..834926f 100644 --- a/amaranth/vendor/_lattice.py +++ b/amaranth/vendor/_lattice.py @@ -686,9 +686,9 @@ class LatticePlatform(TemplatedPlatform): set_hierarchy_separator {/} {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%} {% if port_signal is not none -%} - create_clock -name {{port_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote}}] + create_clock -name {{port_signal.name|tcl_quote("Diamond")}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote("Diamond")}}] {% else -%} - create_clock -name {{net_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_quote}}] + create_clock -name {{net_signal.name|tcl_quote("Diamond")}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_quote("Diamond")}}] {% endif %} {% endfor %} {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}