From 91d45136828c55c2c035cd12ea41dd41ce1c1669 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Fri, 20 Jan 2023 20:48:29 +0100 Subject: [PATCH] Fix several typos. NFC. --- amaranth/_toolchain/cxx.py | 2 +- amaranth/back/rtlil.py | 2 +- amaranth/back/verilog.py | 2 +- amaranth/hdl/ast.py | 2 +- amaranth/lib/io.py | 4 ++-- amaranth/vendor/xilinx.py | 4 ++-- docs/changes.rst | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/amaranth/_toolchain/cxx.py b/amaranth/_toolchain/cxx.py index 1608c0b..a2b7006 100644 --- a/amaranth/_toolchain/cxx.py +++ b/amaranth/_toolchain/cxx.py @@ -12,7 +12,7 @@ def build_cxx(*, cxx_sources, output_name, include_dirs, macros): cwd = os.getcwd() try: - # Unforuntately, `ccompiler.compile` assumes the paths are relative, and interprets + # Unfortunately, `ccompiler.compile` assumes the paths are relative, and interprets # the directory name of the source path specially. That makes it necessary to build in # the output directory directly. os.chdir(build_dir.name) diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py index ec2e7bc..0f43f20 100644 --- a/amaranth/back/rtlil.py +++ b/amaranth/back/rtlil.py @@ -1046,7 +1046,7 @@ def convert_fragment(fragment, name="top", *, emit_src=True): def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=True, **kwargs): # TODO(amaranth-0.4): remove if ports is None: - warnings.warn("Implicit port determination is deprecated, specify ports explictly", + warnings.warn("Implicit port determination is deprecated, specify ports explicitly", DeprecationWarning, stacklevel=2) fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs) il_text, name_map = convert_fragment(fragment, name, emit_src=emit_src) diff --git a/amaranth/back/verilog.py b/amaranth/back/verilog.py index 7a0a8e5..894878d 100644 --- a/amaranth/back/verilog.py +++ b/amaranth/back/verilog.py @@ -45,7 +45,7 @@ def convert_fragment(*args, strip_internal_attrs=False, **kwargs): def convert(elaboratable, name="top", platform=None, ports=None, *, emit_src=True, strip_internal_attrs=False, **kwargs): # TODO(amaranth-0.4): remove if ports is None: - warnings.warn("Implicit port determination is deprecated, specify ports explictly", + warnings.warn("Implicit port determination is deprecated, specify ports explicitly", DeprecationWarning, stacklevel=2) fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs) verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs) diff --git a/amaranth/hdl/ast.py b/amaranth/hdl/ast.py index 60141a3..4dcf4c0 100644 --- a/amaranth/hdl/ast.py +++ b/amaranth/hdl/ast.py @@ -854,7 +854,7 @@ class Cat(Value): Returns ------- Value, inout - Resulting ``Value`` obtained by concatentation. + Resulting ``Value`` obtained by concatenation. """ def __init__(self, *args, src_loc_at=0): super().__init__(src_loc_at=src_loc_at) diff --git a/amaranth/lib/io.py b/amaranth/lib/io.py index 9776eff..b0fb305 100644 --- a/amaranth/lib/io.py +++ b/amaranth/lib/io.py @@ -54,7 +54,7 @@ class Pin(Record): or tristate buffers that may include a 1:n gearbox. (A 1:2 gearbox is typically called "DDR".) A :class:`Pin` is identical to a :class:`Record` that uses the corresponding :meth:`pin_layout` - except that it allos accessing the parameters like ``width`` as attributes. It is legal to use + except that it allows accessing the parameters like ``width`` as attributes. It is legal to use a plain :class:`Record` anywhere a :class:`Pin` is used, provided that these attributes are not necessary. @@ -83,7 +83,7 @@ class Pin(Record): i_clk: I/O buffer input clock. Synchronizes `i*`. Present if ``xdr`` is nonzero. i_fclk: - I/O buffer input fast clock. Synchronizes `i*` on higer gearbox ratios. Present if ``xdr`` + I/O buffer input fast clock. Synchronizes `i*` on higher gearbox ratios. Present if ``xdr`` is greater than 2. i : Signal, out I/O buffer input, without gearing. Present if ``dir="i"`` or ``dir="io"``, and ``xdr`` is diff --git a/amaranth/vendor/xilinx.py b/amaranth/vendor/xilinx.py index e45104b..4adc42a 100644 --- a/amaranth/vendor/xilinx.py +++ b/amaranth/vendor/xilinx.py @@ -654,9 +654,9 @@ class XilinxPlatform(TemplatedPlatform): assert False def create_missing_domain(self, name): - # Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton + # Xilinx devices have a global write enable (GWE) signal that asserted during configuration # and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic - # syncronous to configuration clock, which is not used by most designs), even though it is + # synchronous to configuration clock, which is not used by most designs), even though it is # a low-skew global network, its deassertion may violate a setup/hold constraint with # relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS # signal (if available). For details, see: diff --git a/docs/changes.rst b/docs/changes.rst index 6fa572a..d6a52a2 100644 --- a/docs/changes.rst +++ b/docs/changes.rst @@ -64,7 +64,7 @@ Language changes * Added: :meth:`Value.shift_left` and :meth:`Value.shift_right`. * Added: :class:`ValueCastable`. * Deprecated: :class:`ast.UserValue`; use :class:`ValueCastable` instead. -* Added: Divison and modulo operators can be used with a negative divisor. +* Added: Division and modulo operators can be used with a negative divisor. Standard library changes