diff --git a/nmigen/compat/genlib/resetsync.py b/nmigen/compat/genlib/resetsync.py
index 218dc8a..afd26fb 100644
--- a/nmigen/compat/genlib/resetsync.py
+++ b/nmigen/compat/genlib/resetsync.py
@@ -10,7 +10,7 @@ __all__ = ["AsyncResetSynchronizer"]
             "a clock domain name as an argument, not a clock domain object")
 class CompatResetSynchronizer(NativeResetSynchronizer):
     def __init__(self, cd, async_reset):
-        super().__init__(async_reset, cd.name)
+        super().__init__(async_reset, domain=cd.name)
 
 
 AsyncResetSynchronizer = CompatResetSynchronizer
diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py
index 83b90d8..6d22714 100644
--- a/nmigen/lib/cdc.py
+++ b/nmigen/lib/cdc.py
@@ -70,7 +70,7 @@ class MultiReg(Elaboratable):
 
 
 class ResetSynchronizer(Elaboratable):
-    def __init__(self, arst, domain="sync", n=2):
+    def __init__(self, arst, *, domain="sync", n=2):
         self.arst = arst
         self.domain = domain