diff --git a/amaranth/lib/io.py b/amaranth/lib/io.py
index c1d1e9e..2d94bfb 100644
--- a/amaranth/lib/io.py
+++ b/amaranth/lib/io.py
@@ -477,12 +477,16 @@ class FFBuffer(wiring.Component):
         super().__init__(FFBuffer.Signature(direction, len(port)).flip())
         if self.signature.direction is not Direction.Output:
             self._i_domain = i_domain or "sync"
-        elif i_domain is not None:
-            raise ValueError("Output buffer doesn't have an input domain")
+        else:
+            if i_domain is not None:
+                raise ValueError("Output buffer doesn't have an input domain")
+            self._i_domain = None
         if self.signature.direction is not Direction.Input:
             self._o_domain = o_domain or "sync"
-        elif o_domain is not None:
-            raise ValueError("Input buffer doesn't have an output domain")
+        else:
+            if o_domain is not None:
+                raise ValueError("Input buffer doesn't have an output domain")
+            self._o_domain = None
         if port.direction is Direction.Input and self.direction is not Direction.Input:
             raise ValueError(f"Input port cannot be used with {self.direction.name} buffer")
         if port.direction is Direction.Output and self.direction is not Direction.Output:
@@ -498,14 +502,10 @@ class FFBuffer(wiring.Component):
 
     @property
     def i_domain(self):
-        if self.direction is Direction.Output:
-            raise AttributeError("Output buffer doesn't have an input domain")
         return self._i_domain
 
     @property
     def o_domain(self):
-        if self.direction is Direction.Input:
-            raise AttributeError("Input buffer doesn't have an output domain")
         return self._o_domain
 
     def elaborate(self, platform):
@@ -608,12 +608,16 @@ class DDRBuffer(wiring.Component):
         super().__init__(DDRBuffer.Signature(direction, len(port)).flip())
         if self.signature.direction is not Direction.Output:
             self._i_domain = i_domain or "sync"
-        elif i_domain is not None:
-            raise ValueError("Output buffer doesn't have an input domain")
+        else:
+            if i_domain is not None:
+                raise ValueError("Output buffer doesn't have an input domain")
+            self._i_domain = None
         if self.signature.direction is not Direction.Input:
             self._o_domain = o_domain or "sync"
-        elif o_domain is not None:
-            raise ValueError("Input buffer doesn't have an output domain")
+        else:
+            if o_domain is not None:
+                raise ValueError("Input buffer doesn't have an output domain")
+            self._o_domain = None
         if port.direction is Direction.Input and self.direction is not Direction.Input:
             raise ValueError(f"Input port cannot be used with {self.direction.name} buffer")
         if port.direction is Direction.Output and self.direction is not Direction.Output:
@@ -629,14 +633,10 @@ class DDRBuffer(wiring.Component):
 
     @property
     def i_domain(self):
-        if self.direction is Direction.Output:
-            raise AttributeError("Output buffer doesn't have an input domain")
         return self._i_domain
 
     @property
     def o_domain(self):
-        if self.direction is Direction.Input:
-            raise AttributeError("Input buffer doesn't have an output domain")
         return self._o_domain
 
     def elaborate(self, platform):
diff --git a/tests/test_lib_io.py b/tests/test_lib_io.py
index 6c4de8e..aabf945 100644
--- a/tests/test_lib_io.py
+++ b/tests/test_lib_io.py
@@ -426,19 +426,15 @@ class FFBufferTestCase(FHDLTestCase):
         self.assertIs(buf.port, port)
         self.assertRepr(buf.signature, "FFBuffer.Signature(Direction.Input, 4).flip()")
         self.assertEqual(buf.i_domain, "sync")
-        with self.assertRaisesRegex(AttributeError,
-                r"^Input buffer doesn't have an output domain$"):
-            buf.o_domain
+        self.assertIs(buf.o_domain, None)
         buf = FFBuffer("i", port, i_domain="inp")
         self.assertEqual(buf.i_domain, "inp")
         buf = FFBuffer("o", port)
         self.assertEqual(buf.direction, Direction.Output)
         self.assertIs(buf.port, port)
         self.assertRepr(buf.signature, "FFBuffer.Signature(Direction.Output, 4).flip()")
+        self.assertIs(buf.i_domain, None)
         self.assertEqual(buf.o_domain, "sync")
-        with self.assertRaisesRegex(AttributeError,
-                r"^Output buffer doesn't have an input domain$"):
-            buf.i_domain
         buf = FFBuffer("o", port, o_domain="out")
         self.assertEqual(buf.o_domain, "out")
         buf = FFBuffer("io", port)
@@ -668,19 +664,15 @@ class DDRBufferTestCase(FHDLTestCase):
         self.assertIs(buf.port, port)
         self.assertRepr(buf.signature, "DDRBuffer.Signature(Direction.Input, 4).flip()")
         self.assertEqual(buf.i_domain, "sync")
-        with self.assertRaisesRegex(AttributeError,
-                r"^Input buffer doesn't have an output domain$"):
-            buf.o_domain
+        self.assertIs(buf.o_domain, None)
         buf = DDRBuffer("i", port, i_domain="inp")
         self.assertEqual(buf.i_domain, "inp")
         buf = DDRBuffer("o", port)
         self.assertEqual(buf.direction, Direction.Output)
         self.assertIs(buf.port, port)
         self.assertRepr(buf.signature, "DDRBuffer.Signature(Direction.Output, 4).flip()")
+        self.assertIs(buf.i_domain, None)
         self.assertEqual(buf.o_domain, "sync")
-        with self.assertRaisesRegex(AttributeError,
-                r"^Output buffer doesn't have an input domain$"):
-            buf.i_domain
         buf = DDRBuffer("o", port, o_domain="out")
         self.assertEqual(buf.o_domain, "out")
         buf = DDRBuffer("io", port)