diff --git a/nmigen/compat/genlib/fifo.py b/nmigen/compat/genlib/fifo.py
index 4e412d3..c7d8c36 100644
--- a/nmigen/compat/genlib/fifo.py
+++ b/nmigen/compat/genlib/fifo.py
@@ -1,4 +1,4 @@
-from ...tools import deprecated
+from ...tools import deprecated, extend
 from ...lib.fifo import FIFOInterface as NativeFIFOInterface, \
   SyncFIFO, SyncFIFOBuffered, AsyncFIFO, AsyncFIFOBuffered
 
@@ -14,3 +14,25 @@ class CompatFIFOInterface(NativeFIFOInterface):
 
 
 _FIFOInterface = CompatFIFOInterface
+
+
+@extend(NativeFIFOInterface)
+def read(self):
+    """Read method for simulation."""
+    assert (yield self.r_rdy)
+    value = (yield self.r_data)
+    yield self.r_en.eq(1)
+    yield
+    yield self.r_en.eq(0)
+    yield
+    return value
+
+@extend(NativeFIFOInterface)
+def write(self, data):
+    """Write method for simulation."""
+    assert (yield self.w_rdy)
+    yield self.w_data.eq(data)
+    yield self.w_en.eq(1)
+    yield
+    yield self.w_en.eq(0)
+    yield
diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index 638a77e..9be6003 100644
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -73,23 +73,6 @@ class FIFOInterface:
         self.r_rdy  = Signal() # not empty
         self.r_en   = Signal()
 
-    def read(self):
-        """Read method for simulation."""
-        assert (yield self.r_rdy)
-        yield self.r_en.eq(1)
-        yield
-        value = (yield self.r_data)
-        yield self.r_en.eq(0)
-        return value
-
-    def write(self, data):
-        """Write method for simulation."""
-        assert (yield self.w_rdy)
-        yield self.w_data.eq(data)
-        yield self.w_en.eq(1)
-        yield
-        yield self.w_en.eq(0)
-
     # TODO(nmigen-0.2): move this to nmigen.compat and make it a deprecated extension
     @property
     @deprecated("instead of `fifo.din`, use `fifo.w_data`")
diff --git a/nmigen/test/test_lib_fifo.py b/nmigen/test/test_lib_fifo.py
index 9a8c9c1..93ad95b 100644
--- a/nmigen/test/test_lib_fifo.py
+++ b/nmigen/test/test_lib_fifo.py
@@ -5,42 +5,6 @@ from ..back.pysim import *
 from ..lib.fifo import *
 
 
-class FIFOSmokeTestCase(FHDLTestCase):
-    def assertSyncFIFOWorks(self, fifo, xfrm=lambda x: x):
-        with Simulator(xfrm(Fragment.get(fifo, None)), vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            def process():
-                yield from fifo.write(1)
-                yield from fifo.write(2)
-                while not (yield fifo.r_rdy):
-                    yield
-                if not fifo.fwft:
-                    yield fifo.r_en.eq(1)
-                yield
-                self.assertEqual((yield from fifo.read()), 1)
-                self.assertEqual((yield from fifo.read()), 2)
-            sim.add_sync_process(process)
-            sim.run()
-
-    def assertAsyncFIFOWorks(self, fifo):
-        self.assertSyncFIFOWorks(fifo, xfrm=DomainRenamer({"read": "sync", "write": "sync"}))
-
-    def test_sync_fwft(self):
-        self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=True))
-
-    def test_sync_not_fwft(self):
-        self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=False))
-
-    def test_sync_buffered(self):
-        self.assertSyncFIFOWorks(SyncFIFOBuffered(width=8, depth=4))
-
-    def test_async(self):
-        self.assertAsyncFIFOWorks(AsyncFIFO(width=8, depth=4))
-
-    def test_async_buffered(self):
-        self.assertAsyncFIFOWorks(AsyncFIFOBuffered(width=8, depth=3))
-
-
 class FIFOModel(Elaboratable, FIFOInterface):
     """
     Non-synthesizable first-in first-out queue, implemented naively as a chain of registers.