From b0b193f1ad65d1f4f5c16a4b8249f43b3ea29c9f Mon Sep 17 00:00:00 2001 From: Catherine Date: Tue, 28 Nov 2023 12:14:08 +0000 Subject: [PATCH] sim.pysim: admit non-signals in `write_vcd(traces=...)`. Rather than requiring each additional requested trace to be a signal, all of the signals in the provided value are added to the GTKW file and to the VCD file if they are not already there. This improves usability for `lib.data` as struct fields can now be added to traces. --- amaranth/sim/pysim.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py index f6d3e5c..bc5b1ec 100644 --- a/amaranth/sim/pysim.py +++ b/amaranth/sim/pysim.py @@ -64,9 +64,10 @@ class _VCDWriter: trace_names = SignalDict() for trace in traces: - if trace not in signal_names: - trace_names[trace] = {("bench", trace.name)} - self.traces.append(trace) + for trace_signal in trace._rhs_signals(): + if trace_signal not in signal_names: + trace_names[trace_signal] = {("bench", trace_signal.name)} + self.traces.append(trace_signal) if self.vcd_writer is None: return