diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 0235896..a9836d9 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -121,6 +121,9 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             for bit in range(len(q)):
                 _q = Signal()
                 _q.attrs["IOB"] = "TRUE"
+                # XXX: Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing
+                # unless we prevent it from being optimized.
+                _q.attrs["DONT_TOUCH"] = "TRUE"
                 m.submodules += Instance("FDCE",
                     i_C=clk,
                     i_CE=Const(1),