diff --git a/tests/test_hdl_cd.py b/tests/test_hdl_cd.py
index 4e93fbc..51cf845 100644
--- a/tests/test_hdl_cd.py
+++ b/tests/test_hdl_cd.py
@@ -15,7 +15,7 @@ class ClockDomainTestCase(FHDLTestCase):
         self.assertEqual(pix.clk.name, "pix_clk")
         self.assertEqual(pix.rst.name, "pix_rst")
         cd_pix = ClockDomain()
-        self.assertEqual(pix.name, "pix")
+        self.assertEqual(cd_pix.name, "pix")
         dom = [ClockDomain("foo")][0]
         self.assertEqual(dom.name, "foo")
         with self.assertRaisesRegex(ValueError,