From b9c2404f226ce9bf72c03f2089e5daaba624ba8c Mon Sep 17 00:00:00 2001 From: Catherine Date: Mon, 11 Dec 2023 17:57:34 +0000 Subject: [PATCH] lib.wiring: make values of `In` and `Out` be strings "In" and "Out". Their `str()` and `repr()` values are already that; and the 0 and 1 don't make sense. The RFC leaves it unspecified. --- amaranth/lib/wiring.py | 4 ++-- tests/test_lib_wiring.py | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/amaranth/lib/wiring.py b/amaranth/lib/wiring.py index 18ceb58..e171fb7 100644 --- a/amaranth/lib/wiring.py +++ b/amaranth/lib/wiring.py @@ -15,8 +15,8 @@ __all__ = ["In", "Out", "Signature", "PureInterface", "connect", "flipped", "Com class Flow(enum.Enum): - Out = 0 - In = 1 + Out = "Out" + In = "In" def flip(self): if self == Out: diff --git a/tests/test_lib_wiring.py b/tests/test_lib_wiring.py index 9bdef91..a7ba0e5 100644 --- a/tests/test_lib_wiring.py +++ b/tests/test_lib_wiring.py @@ -26,6 +26,10 @@ class FlowTestCase(unittest.TestCase): self.assertEqual(str(Flow.In), "In") self.assertEqual(str(Flow.Out), "Out") + def test_flow_value(self): + self.assertEqual(Flow.In.value, "In") + self.assertEqual(Flow.Out.value, "Out") + class MemberTestCase(unittest.TestCase): def test_port_member(self):