diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py
index eb32282..a49db77 100644
--- a/nmigen/hdl/ir.py
+++ b/nmigen/hdl/ir.py
@@ -373,9 +373,12 @@ class Fragment:
                 else:
                     assert defs[sig] is self
 
-        def add_io(sig):
-            assert sig not in ios
-            ios[sig] = self
+        def add_io(*sigs):
+            for sig in flatten(sigs):
+                if sig not in ios:
+                    ios[sig] = self
+                else:
+                    assert ios[sig] is self
 
         # Collect all signals we're driving (on LHS of statements), and signals we're using
         # (on RHS of statements, or in clock domains).
@@ -400,8 +403,8 @@ class Fragment:
                         subfrag.add_ports(value._lhs_signals(), dir=dir)
                         add_defs(value._lhs_signals())
                     if dir == "io":
-                        subfrag.add_ports(value, dir=dir)
-                        add_io(value)
+                        subfrag.add_ports(value._lhs_signals(), dir=dir)
+                        add_io(value._lhs_signals())
             else:
                 parent[subfrag] = self
                 level [subfrag] = level[self] + 1
diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py
index 850e5f4..7f03a62 100644
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@@ -603,7 +603,7 @@ class InstanceTestCase(FHDLTestCase):
             i_rst=self.rst,
             o_stb=self.stb,
             o_data=Cat(self.datal, self.datah),
-            io_pins=self.pins
+            io_pins=self.pins[:]
         )
         self.wrap = Fragment()
         self.wrap.add_subfragment(self.inst)