From d1895108c3e61ae7f2b309d970c8b1a2521dcdf6 Mon Sep 17 00:00:00 2001 From: Catherine Date: Fri, 31 May 2024 13:06:14 +0000 Subject: [PATCH] sim: remove dead code. NFC This is a remnant of feature added in commit 11f7b887 and removed in commit 994fa815. --- amaranth/sim/pysim.py | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py index 1a9c876..18021ec 100644 --- a/amaranth/sim/pysim.py +++ b/amaranth/sim/pysim.py @@ -23,7 +23,7 @@ class _VCDWriter: def decode_to_vcd(format, value): return format.format(value).expandtabs().replace(" ", "_") - def __init__(self, state, design, *, vcd_file, gtkw_file=None, traces=(), fs_per_delta=0, processes=()): + def __init__(self, state, design, *, vcd_file, gtkw_file=None, traces=(), fs_per_delta=0): self.state = state self.fs_per_delta = fs_per_delta @@ -236,26 +236,6 @@ class _VCDWriter: vcd_vars.append(row_vcd_vars) gtkw_names.append(row_gtkw_names) - self.vcd_process_vars = {} - if fs_per_delta == 0: - return # Not useful without delta cycle expansion. - for index, process in enumerate(processes): - func_name = process.constructor.__name__ - func_file = os.path.basename(process.constructor.__code__.co_filename) - func_line = process.constructor.__code__.co_firstlineno - for name in ( - f"{process.constructor.__name__}", - f"{process.constructor.__name__}!{func_file};{func_line}", - f"{process.constructor.__name__}#{index}", - ): - try: - self.vcd_process_vars[process] = self.vcd_writer.register_var( - scope=("debug", "proc"), name=name, var_type="string", size=None, - init="(init)") - break - except KeyError: - pass # try another name - def update_signal(self, timestamp, signal): for (vcd_var, repr) in self.vcd_signal_vars.get(signal, ()): if isinstance(repr, Value): @@ -723,8 +703,7 @@ class PySimEngine(BaseEngine): @contextmanager def write_vcd(self, *, vcd_file, gtkw_file, traces, fs_per_delta): vcd_writer = _VCDWriter(self._state, self._design, - vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces, fs_per_delta=fs_per_delta, - processes=self._testbenches) + vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces, fs_per_delta=fs_per_delta) try: self._vcd_writers.append(vcd_writer) yield