diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py index e42d6f4..ec2e7bc 100644 --- a/amaranth/back/rtlil.py +++ b/amaranth/back/rtlil.py @@ -652,6 +652,11 @@ class _LHSValueCompiler(_ValueCompiler): raise TypeError # :nocov: def on_Operator(self, value): + if value.operator in ("u", "s"): + # These operators are transparent on the LHS. + arg, = value.operands + return self(arg) + raise TypeError # :nocov: def match_shape(self, value, new_bits, new_sign): diff --git a/amaranth/hdl/ast.py b/amaranth/hdl/ast.py index cd06063..80e826c 100644 --- a/amaranth/hdl/ast.py +++ b/amaranth/hdl/ast.py @@ -734,6 +734,11 @@ class Operator(Value): raise NotImplementedError("Operator {}/{} not implemented" .format(self.operator, len(op_shapes))) # :nocov: + def _lhs_signals(self): + if self.operator in ("u", "s"): + return union(op._lhs_signals() for op in self.operands) + return super()._lhs_signals() + def _rhs_signals(self): return union(op._rhs_signals() for op in self.operands) diff --git a/amaranth/sim/_pyrtl.py b/amaranth/sim/_pyrtl.py index e1e5ee6..b1d608b 100644 --- a/amaranth/sim/_pyrtl.py +++ b/amaranth/sim/_pyrtl.py @@ -279,6 +279,8 @@ class _LHSValueCompiler(_ValueCompiler): return gen def on_Operator(self, value): + if value.operator in ("u", "s"): + return self(value.operands[0]) raise TypeError # :nocov: def on_Slice(self, value): diff --git a/tests/test_sim.py b/tests/test_sim.py index 72c1764..8447ed4 100644 --- a/tests/test_sim.py +++ b/tests/test_sim.py @@ -62,6 +62,10 @@ class SimulatorUnitTestCase(FHDLTestCase): self.assertStatement(stmt, [C(0b01, signed(2)), C(0b0001, unsigned(4))], C(1)) self.assertStatement(stmt, [C(0b11, signed(2)), C(0b0011, unsigned(4))], C(1)) + def test_as_unsigned_lhs(self): + stmt = lambda y, a: y.as_unsigned().eq(a) + self.assertStatement(stmt, [C(0b01, unsigned(2))], C(0b0001, signed(4))) + def test_as_signed(self): stmt = lambda y, a, b: y.eq(a.as_signed() == b) self.assertStatement(stmt, [C(0b01, unsigned(2)), C(0b0001, signed(4))], C(1)) @@ -72,6 +76,10 @@ class SimulatorUnitTestCase(FHDLTestCase): self.assertStatement(stmt, [C(0b01, unsigned(2))], C(0b0001, signed(4))) self.assertStatement(stmt, [C(0b11, unsigned(2))], C(0b1111, signed(4))) + def test_as_signed_lhs(self): + stmt = lambda y, a: y.as_signed().eq(a) + self.assertStatement(stmt, [C(0b01, unsigned(2))], C(0b0001, signed(4))) + def test_any(self): stmt = lambda y, a: y.eq(a.any()) self.assertStatement(stmt, [C(0b00, 2)], C(0))