diff --git a/docs/_code/up_counter.py b/docs/_code/up_counter.py
index 3ab1f4f..e73cab8 100644
--- a/docs/_code/up_counter.py
+++ b/docs/_code/up_counter.py
@@ -1,7 +1,9 @@
 from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
 
 
-class UpCounter(Elaboratable):
+class UpCounter(wiring.Component):
     """
     A 16-bit up counter with a fixed limit.
 
@@ -18,16 +20,16 @@ class UpCounter(Elaboratable):
     ovf : Signal, out
         ``ovf`` is asserted when the counter reaches its limit.
     """
+
+    en: In(1)
+    ovf: Out(1)
+
     def __init__(self, limit):
         self.limit = limit
-
-        # Ports
-        self.en  = Signal()
-        self.ovf = Signal()
-
-        # State
         self.count = Signal(16)
 
+        super().__init__()
+
     def elaborate(self, platform):
         m = Module()
 
@@ -76,4 +78,4 @@ from amaranth.back import verilog
 
 top = UpCounter(25)
 with open("up_counter.v", "w") as f:
-    f.write(verilog.convert(top, ports=[top.en, top.ovf]))
+    f.write(verilog.convert(top))
diff --git a/docs/_code/up_counter.v b/docs/_code/up_counter.v
index 8a5b330..7f394ae 100644
--- a/docs/_code/up_counter.v
+++ b/docs/_code/up_counter.v
@@ -1,48 +1,49 @@
 (* generator = "Amaranth" *)
-module top(clk, rst, en, ovf);
-  (* src = "<amaranth-root>/amaranth/hdl/ir.py:526" *)
-  input clk;
-  (* src = "<amaranth-root>/amaranth/hdl/ir.py:526" *)
-  input rst;
-  (* src = "up_counter.py:26" *)
-  input en;
-  (* src = "up_counter.py:27" *)
-  output ovf;
-  (* src = "up_counter.py:30" *)
-  reg [15:0] count = 16'h0000;
-  (* src = "up_counter.py:30" *)
-  reg [15:0] \count$next ;
-  (* src = "up_counter.py:35" *)
+module top(ovf, clk, rst, en);
+  reg \$auto$verilog_backend.cc:2255:dump_module$1  = 0;
+  (* src = "up_counter.py:36" *)
   wire \$1 ;
-  (* src = "up_counter.py:41" *)
+  (* src = "up_counter.py:42" *)
   wire [16:0] \$3 ;
-  (* src = "up_counter.py:41" *)
+  (* src = "up_counter.py:42" *)
   wire [16:0] \$4 ;
-  assign \$1  = count == (* src = "up_counter.py:35" *) 5'h19;
-  assign \$4  = count + (* src = "up_counter.py:41" *) 1'h1;
+  (* src = "<site-packages>/amaranth/hdl/ir.py:509" *)
+  input clk;
+  wire clk;
+  (* src = "up_counter.py:29" *)
+  reg [15:0] count = 16'h0000;
+  (* src = "up_counter.py:29" *)
+  reg [15:0] \count$next ;
+  (* src = "<site-packages>/amaranth/lib/wiring.py:1647" *)
+  input en;
+  wire en;
+  (* src = "<site-packages>/amaranth/lib/wiring.py:1647" *)
+  output ovf;
+  wire ovf;
+  (* src = "<site-packages>/amaranth/hdl/ir.py:509" *)
+  input rst;
+  wire rst;
+  assign \$1  = count == (* src = "up_counter.py:36" *) 5'h19;
+  assign \$4  = count + (* src = "up_counter.py:42" *) 1'h1;
   always @(posedge clk)
-      count <= \count$next ;
+    count <= \count$next ;
   always @* begin
+    if (\$auto$verilog_backend.cc:2255:dump_module$1 ) begin end
     \count$next  = count;
-    (* src = "up_counter.py:37" *)
-    casez (en)
-      /* src = "up_counter.py:37" */
-      1'h1:
-          (* src = "up_counter.py:38" *)
-          casez (ovf)
-            /* src = "up_counter.py:38" */
-            1'h1:
-                \count$next  = 16'h0000;
-            /* src = "up_counter.py:40" */
-            default:
-                \count$next  = \$3 [15:0];
-          endcase
-    endcase
-    (* src = "<amaranth-root>/amaranth/hdl/xfrm.py:518" *)
-    casez (rst)
-      1'h1:
-          \count$next  = 16'h0000;
-    endcase
+    (* src = "up_counter.py:38" *)
+    if (en) begin
+      (* full_case = 32'd1 *)
+      (* src = "up_counter.py:39" *)
+      if (ovf) begin
+        \count$next  = 16'h0000;
+      end else begin
+        \count$next  = \$4 [15:0];
+      end
+    end
+    (* src = "<site-packages>/amaranth/hdl/xfrm.py:534" *)
+    if (rst) begin
+      \count$next  = 16'h0000;
+    end
   end
   assign \$3  = \$4 ;
   assign ovf = \$1 ;
diff --git a/docs/start.rst b/docs/start.rst
index 3d7772f..0be3a76 100644
--- a/docs/start.rst
+++ b/docs/start.rst
@@ -27,7 +27,7 @@ A 16-bit up counter with enable input, overflow output, and a limit fixed at des
    :lineno-match:
    :end-before: # --- TEST ---
 
-The reusable building block of Amaranth designs is an ``Elaboratable``: a Python class that includes HDL signals (``en`` and ``ovf``, in this case) as a part of its interface, and provides the ``elaborate`` method that defines its behavior.
+The reusable building block of Amaranth designs is a ``Component``: a Python class declares its interface (``en`` and ``ovf``, in this case) and implements the ``elaborate`` method that defines its behavior.
 
 .. TODO: link to Elaboratable reference