From ee9da63287c1ea5b478f93ca9624f1449e3c4d0c Mon Sep 17 00:00:00 2001 From: Irides Date: Tue, 5 Apr 2022 15:43:30 -0500 Subject: [PATCH] build/plat: implement an override disabling debug Verilog generation. Currently debug Verilog generation can take many 10's of seconds. A new override can now be passed as `AMARANTH_debug_verilog`=0 on the environment or by setting the `debug_verilog` keyword argument to `Platform.build()` or `Platform.prepare_toolchain()` to `False`. Fixes #623. --- amaranth/build/plat.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/amaranth/build/plat.py b/amaranth/build/plat.py index 4b922a9..3b706ab 100644 --- a/amaranth/build/plat.py +++ b/amaranth/build/plat.py @@ -367,8 +367,11 @@ class TemplatedPlatform(Platform): strip_internal_attrs=True, write_verilog_opts=opts) def emit_debug_verilog(opts=()): - return verilog._convert_rtlil_text(rtlil_text, - strip_internal_attrs=False, write_verilog_opts=opts) + if not get_override_flag("debug_verilog"): + return "/* Debug Verilog generation was disabled. */" + else: + return verilog._convert_rtlil_text(rtlil_text, + strip_internal_attrs=False, write_verilog_opts=opts) def emit_commands(syntax): commands = []