diff --git a/amaranth/vendor/_siliconblue.py b/amaranth/vendor/_siliconblue.py
index 08cc966..0db8380 100644
--- a/amaranth/vendor/_siliconblue.py
+++ b/amaranth/vendor/_siliconblue.py
@@ -507,12 +507,12 @@ class SiliconBluePlatform(TemplatedPlatform):
                 else:
                     io_args.append(("o", "D_IN_0", i[bit]))
             elif isinstance(buffer, io.FFBuffer):
-                m.submodules += RequirePosedge(self.i_domain)
+                m.submodules += RequirePosedge(buffer.i_domain)
                 i_type =     0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
                 io_args.append(("i", "INPUT_CLK", ClockSignal(buffer.i_domain)))
                 io_args.append(("o", "D_IN_0", i[bit]))
             elif isinstance(buffer, io.DDRBuffer):
-                m.submodules += RequirePosedge(self.i_domain)
+                m.submodules += RequirePosedge(buffer.i_domain)
                 i_type =     0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
                 io_args.append(("i", "INPUT_CLK", ClockSignal(buffer.i_domain)))
                 io_args.append(("o", "D_IN_0", i0[bit]))
@@ -524,12 +524,12 @@ class SiliconBluePlatform(TemplatedPlatform):
                 o_type = 0b1010   # PIN_OUTPUT_TRISTATE
                 io_args.append(("i", "D_OUT_0", o[bit]))
             elif isinstance(buffer, io.FFBuffer):
-                m.submodules += RequirePosedge(self.o_domain)
+                m.submodules += RequirePosedge(buffer.o_domain)
                 o_type = 0b1101   # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
                 io_args.append(("i", "OUTPUT_CLK", ClockSignal(buffer.o_domain)))
                 io_args.append(("i", "D_OUT_0", o[bit]))
             elif isinstance(buffer, io.DDRBuffer):
-                m.submodules += RequirePosedge(self.o_domain)
+                m.submodules += RequirePosedge(buffer.o_domain)
                 o_type = 0b1100   # PIN_OUTPUT_DDR_ENABLE_REGISTERED
                 io_args.append(("i", "OUTPUT_CLK", ClockSignal(buffer.o_domain)))
                 io_args.append(("i", "D_OUT_0", o0[bit]))