From f49074f439f8a017a2e119cda4bc1d2d141ddda8 Mon Sep 17 00:00:00 2001 From: Catherine Date: Thu, 30 May 2024 21:56:49 +0000 Subject: [PATCH] vendor._siliconblue: unbreak IO buffer instantiation. Bug introduced in 028d5d807 via copy/paste. --- amaranth/vendor/_siliconblue.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/amaranth/vendor/_siliconblue.py b/amaranth/vendor/_siliconblue.py index 08cc966..0db8380 100644 --- a/amaranth/vendor/_siliconblue.py +++ b/amaranth/vendor/_siliconblue.py @@ -507,12 +507,12 @@ class SiliconBluePlatform(TemplatedPlatform): else: io_args.append(("o", "D_IN_0", i[bit])) elif isinstance(buffer, io.FFBuffer): - m.submodules += RequirePosedge(self.i_domain) + m.submodules += RequirePosedge(buffer.i_domain) i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR io_args.append(("i", "INPUT_CLK", ClockSignal(buffer.i_domain))) io_args.append(("o", "D_IN_0", i[bit])) elif isinstance(buffer, io.DDRBuffer): - m.submodules += RequirePosedge(self.i_domain) + m.submodules += RequirePosedge(buffer.i_domain) i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR io_args.append(("i", "INPUT_CLK", ClockSignal(buffer.i_domain))) io_args.append(("o", "D_IN_0", i0[bit])) @@ -524,12 +524,12 @@ class SiliconBluePlatform(TemplatedPlatform): o_type = 0b1010 # PIN_OUTPUT_TRISTATE io_args.append(("i", "D_OUT_0", o[bit])) elif isinstance(buffer, io.FFBuffer): - m.submodules += RequirePosedge(self.o_domain) + m.submodules += RequirePosedge(buffer.o_domain) o_type = 0b1101 # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED io_args.append(("i", "OUTPUT_CLK", ClockSignal(buffer.o_domain))) io_args.append(("i", "D_OUT_0", o[bit])) elif isinstance(buffer, io.DDRBuffer): - m.submodules += RequirePosedge(self.o_domain) + m.submodules += RequirePosedge(buffer.o_domain) o_type = 0b1100 # PIN_OUTPUT_DDR_ENABLE_REGISTERED io_args.append(("i", "OUTPUT_CLK", ClockSignal(buffer.o_domain))) io_args.append(("i", "D_OUT_0", o0[bit]))