diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py
index a3c07cf..3c1275a 100644
--- a/amaranth/sim/pysim.py
+++ b/amaranth/sim/pysim.py
@@ -616,6 +616,10 @@ class PySimEngine(BaseEngine):
             testbench.reset()
 
     def add_clock_process(self, clock, *, phase, period):
+        slot = self.state.get_signal(clock)
+        if self.state.slots[slot].is_comb:
+            raise DriverConflict("Clock signal is already driven by combinational logic")
+
         self._processes.add(PyClockProcess(self._state, clock,
                                            phase=phase, period=period))
 
diff --git a/tests/test_sim.py b/tests/test_sim.py
index 94631a9..b681683 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -1497,6 +1497,15 @@ class SimulatorRegressionTestCase(FHDLTestCase):
         sim.add_testbench(testbench)
         sim.run()
 
+    def test_comb_clock_conflict(self):
+        c = Signal()
+        m = Module()
+        m.d.comb += ClockSignal().eq(c)
+        sim = Simulator(m)
+        with self.assertRaisesRegex(DriverConflict,
+                r"^Clock signal is already driven by combinational logic$"):
+            sim.add_clock(1e-6)
+
     def test_sample(self):
         m = Module()
         m.domains.sync = cd_sync = ClockDomain()