from .tools import *
from ..hdl.ast import *
from ..back.pysim import *
from ..lib.cdc import *


class MultiRegTestCase(FHDLTestCase):
    def test_basic(self):
        i = Signal()
        o = Signal()
        frag = MultiReg(i, o)
        with Simulator(frag) as sim:
            sim.add_clock(1e-6)
            def process():
                self.assertEqual((yield o), 0)
                yield i.eq(1)
                yield Tick()
                self.assertEqual((yield o), 0)
                yield Tick()
                self.assertEqual((yield o), 0)
                yield Tick()
                self.assertEqual((yield o), 1)
            sim.add_process(process)

    def test_basic(self):
        i = Signal(reset=1)
        o = Signal()
        frag = MultiReg(i, o, reset=1)
        with Simulator(frag) as sim:
            sim.add_clock(1e-6)
            def process():
                self.assertEqual((yield o), 1)
                yield i.eq(0)
                yield Tick()
                self.assertEqual((yield o), 1)
                yield Tick()
                self.assertEqual((yield o), 1)
                yield Tick()
                self.assertEqual((yield o), 0)
            sim.add_process(process)