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add GateMate backend
2025-08-18 19:15:16 +02:00
.github CI: fix schema publishing. 2024-05-10 13:44:44 +00:00
amaranth add GateMate backend 2025-08-18 19:15:16 +02:00
docs Release version 0.5. 2024-06-14 19:41:03 +00:00
examples examples: convert to async simulator syntax. 2024-06-10 10:34:32 +00:00
tests backends: s/ilang/rtlil as a result of https://github.com/YosysHQ/yosys/pull/4704 2025-08-18 17:46:28 +02:00
.codecov.yml CI: disable codecov project status. 2020-10-25 00:13:39 +00:00
.coveragerc pyproject: write XML coverage after running the testsuite. 2024-05-06 11:09:46 +00:00
.editorconfig editorconfig: use 2-space indentation for YAML. 2024-05-22 01:05:23 +00:00
.env.toolchain pyproject: use yowasp-yosys for tests. 2023-09-27 11:17:29 +00:00
.gitattributes pyproject: migrate to PDM build backend. 2023-09-12 01:40:48 +00:00
.gitignore Implement RFC 30: Component metadata. 2024-05-10 13:17:24 +00:00
CONTRIBUTING.txt Ensure we build sensible sdists. 2024-02-13 12:52:05 +00:00
LICENSE.txt compat: remove. 2023-12-13 11:20:12 +00:00
pdm_build.py pyproject: use .dev{distance}, not +{node}, for non-release builds. 2024-04-13 12:45:05 +00:00
pyproject.toml Implement RFC 61: Minimal streams. 2024-06-14 18:51:38 +00:00
README.md vendor._lattice: add Nexus support. 2024-04-19 16:01:30 +00:00

Amaranth HDL (previously nMigen)

The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions, a System on Chip toolkit, and more. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components.

The Amaranth toolchain consists of the Amaranth hardware definition language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designers choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow.

The development of Amaranth has been supported by LambdaConcept, ChipEleven, and Chipflow.

Introduction

See the Introduction section of the documentation.

Installation

See the Installation section of the documentation.

Usage

See the Language guide section of the documentation.

Platform support

Amaranth can be used to target any FPGA or ASIC process that accepts behavioral Verilog-2001 as input. It also offers extended support for many FPGA families, providing toolchain integration, abstractions for device-specific primitives, and more. Specifically:

  • Lattice iCE40 (toolchains: Yosys+nextpnr, LSE-iCECube2, Synplify-iCECube2);
  • Lattice MachXO2, MachXO3L (toolchains: Yosys+nextpnr, Diamond);
  • Lattice ECP5 (toolchains: Yosys+nextpnr, Diamond);
  • Lattice Nexus (toolchains: Yosys+nextpnr, Radiant);
  • AMD Virtex, Virtex E, Spartan 2, Spartan 2E (toolchains: ISE);
  • AMD Virtex II, Virtex II Pro (toolchains: ISE);
  • AMD Spartan 3, Spartan 3E, Spartan 3A, Spartan 3AN, Spartan 3A DSP (toolchains: ISE);
  • AMD Virtex 4, Virtex 5, Virtex 6 (toolchains: ISE);
  • AMD Spartan 6 (toolchains: ISE);
  • AMD 7-series (toolchains: Vivado, ISE);
  • AMD UltraScale, UltraScale+ (toolchains: Vivado);
  • Altera (toolchains: Quartus);
  • Quicklogic EOS S3 (toolchains: Yosys+VPR).

FOSS toolchains are listed in bold.

Community

Amaranth has a dedicated IRC channel, #amaranth-lang at libera.chat, which is bridged1 to Matrix at #amaranth-lang:matrix.org. Feel free to join to ask questions about using Amaranth or discuss ongoing development of Amaranth and its related projects.

License

Amaranth is released under the two-clause BSD license. You are permitted to use Amaranth for open-source and proprietary designs provided that the copyright notice in the license file is reproduced.


  1. The same messages appear on IRC and on Matrix, and one can participate in the discussion equally using either communication system. ↩︎