30 lines
918 B
Python
30 lines
918 B
Python
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from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog
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class ALU:
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def __init__(self, width):
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self.sel = Signal(2)
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self.a = Signal(width)
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self.b = Signal(width)
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self.o = Signal(width)
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self.co = Signal()
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def get_fragment(self, platform):
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f = Module()
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with f.If(self.sel == 0b00):
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f.comb += self.o.eq(self.a | self.b)
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with f.Elif(self.sel == 0b01):
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f.comb += self.o.eq(self.a & self.b)
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with f.Elif(self.sel == 0b10):
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f.comb += self.o.eq(self.a ^ self.b)
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with f.Else():
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f.comb += Cat(self.o, self.co).eq(self.a - self.b)
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return f.lower(platform)
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alu = ALU(width=16)
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frag = alu.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]))
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print(verilog.convert(frag, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]))
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