23 lines
680 B
Python
23 lines
680 B
Python
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from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog
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class ClockDivisor:
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def __init__(self, factor):
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self.v = Signal(factor, reset=2**factor-1)
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self.o = Signal()
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self.ce = Signal()
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def get_fragment(self, platform):
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f = Module()
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f.sync += self.v.eq(self.v + 1)
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f.comb += self.o.eq(self.v[-1])
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return CEInserter(self.ce)(f.lower())
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sys = ClockDomain()
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ctr = ClockDivisor(factor=16)
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frag = ctr.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
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print(verilog.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
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