31 lines
938 B
Python
31 lines
938 B
Python
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from nmigen import *
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from nmigen.back import rtlil, verilog
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class RegisterFile:
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def __init__(self):
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self.adr = Signal(4)
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self.dat_r = Signal(8)
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self.dat_w = Signal(8)
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self.we = Signal()
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self.mem = Memory(width=8, depth=16, init=[0xaa, 0x55])
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def get_fragment(self, platform):
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m = Module()
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m.submodules.rdport = rdport = self.mem.read_port()
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m.submodules.wrport = wrport = self.mem.write_port()
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m.d.comb += [
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rdport.addr.eq(self.adr),
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self.dat_r.eq(rdport.data),
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wrport.addr.eq(self.adr),
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wrport.data.eq(self.dat_w),
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wrport.en.eq(self.we),
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]
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return m.lower(platform)
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rf = RegisterFile()
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frag = rf.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we]))
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print(verilog.convert(frag, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we]))
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