41 lines
1.2 KiB
Python
41 lines
1.2 KiB
Python
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from .tools import *
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from ..hdl.ast import *
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from ..back.pysim import *
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from ..lib.cdc import *
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class MultiRegTestCase(FHDLTestCase):
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def test_basic(self):
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i = Signal()
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o = Signal()
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frag = MultiReg(i, o)
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with Simulator(frag) as sim:
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 0)
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yield i.eq(1)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick()
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self.assertEqual((yield o), 1)
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sim.add_process(process)
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def test_basic(self):
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i = Signal(reset=1)
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o = Signal()
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frag = MultiReg(i, o, reset=1)
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with Simulator(frag) as sim:
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 0)
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sim.add_process(process)
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