2018-12-12 03:12:35 -07:00
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from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog
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from nmigen.genlib.cdc import *
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i, o = Signal(name="i"), Signal(name="o")
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frag = MultiReg(i, o).get_fragment(platform=None)
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2018-12-13 04:01:03 -07:00
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# print(rtlil.convert(frag, ports=[i, o]))
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print(verilog.convert(frag, ports=[i, o]))
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