27 lines
709 B
Python
27 lines
709 B
Python
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from nmigen import *
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from nmigen.back import rtlil, verilog
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class System:
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def __init__(self):
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self.adr = Signal(16)
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self.dat_r = Signal(8)
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self.dat_w = Signal(8)
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self.we = Signal()
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def get_fragment(self, platform):
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m = Module()
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m.submodules += Instance("CPU",
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p_RESET_ADDR=0xfff0,
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i_d_adr =self.adr,
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i_d_dat_r=self.dat_r,
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o_d_dat_w=self.dat_w,
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)
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return m.lower(platform)
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sys = System()
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frag = sys.get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we]))
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print(verilog.convert(frag, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we]))
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