11 lines
354 B
Python
11 lines
354 B
Python
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from nmigen.fhdl import *
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from nmigen.back import rtlil, verilog
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from nmigen.genlib.cdc import *
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sys = ClockDomain()
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i, o = Signal(name="i"), Signal(name="o")
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frag = MultiReg(i, o).get_fragment(platform=None)
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# print(rtlil.convert(frag, ports=[i, o], clock_domains={"sys": sys}))
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print(verilog.convert(frag, ports=[i, o], clock_domains={"sys": sys}))
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