2019-01-14 09:50:04 -07:00
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from nmigen import *
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from nmigen.cli import main
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pin = Signal()
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pin_t = TSTriple()
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m = Module()
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m.submodules += pin_t.get_tristate(pin)
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if __name__ == "__main__":
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2019-01-26 09:25:05 -07:00
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main(m, ports=[pin, pin_t.oe, pin_t.i, pin_t.o])
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