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hdl.{ast,dsl},back.rtlil: track source locations for switch cases.

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This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
This commit is contained in:
whitequark 2019-07-09 19:18:02 +00:00
parent 62b3e36612
commit 00c5209a47
4 changed files with 44 additions and 12 deletions
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13
nmigen/back/rtlil.py
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@ -196,7 +196,8 @@ class _SwitchBuilder(_ProxiedBuilder, _AttrBuilder):
def __exit__(self, *args):
self._append("{}end\n", " " * self.indent)
def case(self, *values):
def case(self, *values, attrs={}, src=""):
self._attributes(attrs, src=src, indent=self.indent + 1)
if values == ():
self._append("{}case\n", " " * (self.indent + 1))
else:
@ -602,10 +603,10 @@ class _StatementCompiler(xfrm.StatementVisitor):
self._has_rhs = False
@contextmanager
def case(self, switch, values):
def case(self, switch, values, src=""):
try:
old_case = self._case
with switch.case(*values) as self._case:
with switch.case(*values, src=src) as self._case:
yield
finally:
self._case = old_case
@ -658,7 +659,11 @@ class _StatementCompiler(xfrm.StatementVisitor):
with self._case.switch(test_sigspec, src=src(stmt.src_loc)) as switch:
for values, stmts in stmt.cases.items():
with self.case(switch, values):
if values in stmt.case_src_locs:
case_src = src(stmt.case_src_locs[values])
else:
case_src = ""
with self.case(switch, values, src=case_src):
self.on_statements(stmts)
def on_statement(self, stmt):